An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices

📋 论文概要

本文提出了一种8T eNVSRAM宏单元，在22nm FDSOI标准逻辑工艺中实现，旨在解决超低功耗IoT设备在待机时的高泄漏能耗问题。该设计通过同时全阵列数据恢复功能，在电源关闭前快速保存数据，并兼容标准CMOS逻辑工艺，无需额外制造步骤。

💡 主要创新点

• 提出8T单元结构，在标准逻辑工艺中实现非易失性存储，无需传统EEPROM/FLASH的额外工艺步骤。
• 实现同时全阵列数据恢复，提高了数据恢复速度和安全性，适用于电源突发中断场景。
• 采用22nm FDSOI工艺，利用背栅偏置优化漏电和性能，降低待机功耗。

🏷 关键词

📄 原文摘要

There has been an increasing demand for ultra-low power IoT devices in recent years. These devices often have low activity rates and most of the time are in standby mode, resulting in a high leakage energy consumption. To reduce the leakage energy, the supply power can be turned off, but before doing so, data needs to be stored in a non-volatile memory (NVM). Also, many IoT devices are battery-operated or powered wirelessly and their data needs to be stored before a power-loss event. The conventional NVMs, such as EEPROM and FLASH, are not CMOS-logic compatible in terms of technology node and operating voltages. They also require extra fabrication steps, which increases the cost for IoT devices that use small memories. Furthermore, most NVMs are not embedded with logic. Embedding NVM with logic enables novel architectures, such as in-SRAM nonvolatile weight storage for compute-in-memory (nvCIM). To address these

👥 作者与机构

Sepideh Nouri, Subramanian S. Iyer

University of California, Los Angeles, CA