A 0.96pJ/b 7×50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies

📋 论文概要

该论文提出了一种基于堆叠7nm CMOS和45nm硅光子芯片的波分复用（WDM）接收机，实现了每根光纤7×50Gb/s的传输速率和0.96pJ/b的能效。解决了数据中心中分布式计算架构对高带宽、低功耗光学互连的需求。

💡 主要创新点

• 采用堆叠7nm CMOS与45nm硅光子芯片的异构集成，优化了信号完整性和功耗。
• 实现了每根光纤7通道WDM接收，每通道50Gb/s，总速率350Gb/s，能效仅0.96pJ/b。

🏷 关键词

📄 原文摘要

Ying Cao1, Jae Wook Kim1, Nakul Narang2, Hongyuan Zhao2, Yipeng Wang2, Kee Hian Tan2, Winson Lin1, Jay Im1, David Mahashin1, Santiago Asuncion1, Parag Upadhyaya1, Yohan Frans1 AMD, San Jose, CA AMD, Singapore, Singapore 1 2 Emerging applications such as machine learning, high-performance computing, and cloud storage continue to push compute demands at the data center. To keep up, distributed computing architectures are being increasingly adopted where the physical locations of the CPU, GPU, FPGA, memory, and storage may span over several meters. In package silicon-photonics-based optical links with wavelength division multiplexing (WDM) and non-return-to-zero (NRZ) signaling provides a power-efficient, highbandwidth, and low-latency interface between these components. In this paper, we present a low-power (0.96pJ/b), high-sensitivity (-11.1dBm median), high-bandwidth (7×50Gb/s NRZ WDM) receiver (RX) that achieves <1e-12 bit-error-rate (BER) without

👥 作者与机构

Mayank Raj1, Chuan Xie1, Ade Bekele1, Adam Chou1, Wenfeng Zhang1,