A Scalable Heterogeneous Integrated Two-Stage Vertical Power-Delivery Architecture for High-Performance Computing

📋 论文概要

该论文提出一种可扩展的异构集成两级垂直功率传输架构，用于高性能计算。该架构通过垂直集成电压调节模块和全集成稳压器，解决了大规模峰值电流下低电压供电的I²R损耗问题，无需传统横向布局。

💡 主要创新点

• 创新地采用垂直堆叠的两级功率传输架构，将VRM和FIVR异构集成，减少横向布线损耗。
• 架构具有可扩展性，适用于数据中心、自动驾驶和移动设备等多种高计算需求场景。

🏷 关键词

📄 原文摘要

computing needs in data center, autonomous vehicle, and mobile device processors demand increasingly large peak currents at scaled-CMOScompatible voltages (<1V). To ease otherwise high I2R losses in power delivery (PD), most applications now target high system-level voltage busses (e.g., 20V) prior to arriving at the processor load. However, voltage incompatibility with scaled CMOS means that conventional approaches require a voltage regulator module (VRM) located laterally off-chip [1] for conversion down to a lower rail (e.g., 1.8V), followed by a fully integrated voltage regulator (FIVR) using external LC filters with inductors embedded into the package substrate [2] (Fig. 11.1.1). The large conversion ratio required by the VRM and

👥 作者与机构

Casey Hardy1, Hieu Pham1, Mohamed Mehdi Jatlaoui2, Frederic Voiron2,

Tianshi Xie1, Po-Han Chen1, Saket Jha1, Patrick Mercier1, Hanh-Phuc Le1 University of California, San Diego, CA Murata, Caen, France 1 2 Emerging high-performance