A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations

📋 论文概要

本文提出了一种1.8GHz 12位预采样流水线ADC，通过参考缓冲器和运算放大器功耗松弛技术，在保持高速采样的同时降低了功耗。该设计旨在解决直接射频采样中ADC对SNDR和速度的严苛要求，以及时间交织ADC的校准复杂度和能效问题。

💡 主要创新点

• 采用预采样技术减少采样保持电路对运算放大器的压力，从而允许放大器功耗松弛。
• 通过参考缓冲器优化设计，降低参考电压建立时间与噪声，提升整体线性度。

🏷 关键词

📄 原文摘要

Direct RF sampling reduces complexity for receiver design. However, SNDR and speed specifications of its ADCs are stringent, which makes the time-interleaved (TI) ADC attractive for the required sampling rate. There is a tradeoff between single-channel performance and the complexity of TI calibration. The energy efficiency is also compromised by a high-speed single-channel ADC design. The TI SAR ADC [1] simplifies the single-channel architecture (SAR) with complex skew and inter-channel calibrations. Owing to the lack of a gain stage for noise relaxation, the comparator noise of a SAR ADC limits SNDR. With a gain stage implemented by the ring amplifier [2], the singlechannel closed-loop pipelined ADC speed and SNDR are improved, relaxing the TI calibration. However, the high-power background calibration for the stringent OP finite gain error is inevitable. The pipelined SAR ADC with an open-loop amplifier [3] shows

👥 作者与机构

Sung-En Hsieh, Tzu-Chien Wu, Chun-Chih Hou

MediaTek, Hsinchu, Taiwan