Wafer-Level Stacking of High-Density Capacitors to Enhance the Performance of a Large Multicore Processor for Machine Learning Applications

📋 论文概要

本文提出通过晶圆级堆叠高密度电容（约750µF）与大型多核处理器晶圆融合，显著降低电源电压下冲和过冲，从而提升处理器性能。该方案采用TSMC N7 CMOS和0.13µm Deep Trench Capacitor技术，实现了822mm²的Colossus Mk2x芯片。

💡 主要创新点

• 晶圆级堆叠高密度电容与处理器晶圆直接融合，无需额外封装步骤，有效改善电源完整性。
• 利用TSMC N7工艺和0.13µm深沟槽电容技术，在保持高性能的同时大幅降低电压波动。
• 通过堆叠电容提供约750µF的片上去耦电容，为处理器提供更多电压余量，支持更高频率或更低功耗。

🏷 关键词

📄 原文摘要

Graphcore, Bristol, United Kingdom Graphcore, Adelaide, Australia 1 2 The 822mm2 Colossus Mk2x is a chip made by stacking and fusing two separately processed 12-inch wafers prior to probe-test, singulation and packaging. The two wafers are manufactured using TSMC’s N7 CMOS technology and TSMC’s 0.13µm Deep Trench Capacitor (DTC) technology, respectively. Each N7 die has over 60 billion transistors (typically 1 to 3 fins each), 82% of which constitute >8Gb of SRAM. The circa-750µF stacked capacitor die significantly reduces worst-case supply voltage undershoot and overshoot allowing headroom for the supply voltage to be elevated and a 40% increase in clock speed to achieve a peak performance of 700TFLOPS FP8 arithmetic (350TFLOPS FP16) that occurs when executing large, distributed matrix multiplications using all threads on all tile CPUs. For example, this scenario arises when executing the FFN (Feed

👥 作者与机构

Stephen Felix1, Shannon Morton2, Simon Stacey1, John Walsh1