A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL

📋 论文概要

本文提出了一款1.1V供电、6.4Gb/s/pin数据速率、24Gb容量的DDR5 SDRAM，通过高精度占空比校正器和抗NBTI的DLL设计，解决了高速低功耗下PVT敏感性问题，实现了高密度与高速接口。

💡 主要创新点

• 提出高精度占空比校正器，有效补偿占空比失真，提升信号完整性。
• 设计抗NBTI（负偏置温度不稳定性）的DLL，增强长期可靠性，降低时序抖动。

🏷 关键词

📄 原文摘要

Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jungbum Shin, Yanggyoon Loh, Chang Yong Lee, Junmyung Woo, Hyeseung Yu, Changhyun Bae, Reum Oh, Young-soo Sohn, Changsik Yoo, Jooyoung Lee Samsung Electronics, Hwaseong, Korea The need for high-quality multi-media data increases the amount of data to be stored and processed, necessitating DDR5 to achieve high-density and high-speed with lowpower consumption [1]. However, high-speed with low-power operation makes DRAM more vulnerable to process-voltage-temperature (PVT) variations, negative-bias thermal instability (NBTI), etc. In this work, a mono-die based 24-Gb high-density DDR5 achieving 6.4Gbps/pin is implemented. To lower power consumption, GIO switching is reduced by using a GIO separation switch and a read-only GIO pre-charge scheme. The proposed DRAM has a higher tolerance to NBTI, since the delay-locked loop (DLL)

👥 作者与机构

Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim,