A Single-Channel 10GS/s 8b >36.4dB SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS

📋 论文概要

提出了一种单通道10GS/s 8位时间域ADC，采用循环展开异步逐次逼近技术，解决了多比特决策等待时间长的问题，实现了>36.4dB SNDR。

💡 主要创新点

• 提出循环展开异步逐次逼近技术，减少多比特决策的等待时间，提升时间域ADC的速度。
• 在单通道架构下实现10GS/s采样率，兼顾能量效率和面积效率。

🏷 关键词

📄 原文摘要

Kun Gao Xinxin Technologies, Singapore, Singapore *Equally Credited Authors (ECAs) 1 2 High data throughput and wideband network communications demand high-speed (several to tens of GS/s), moderate-resolution (6-10b) ADCs. The emerging time-domain ADC (TD-ADC) has been gaining more interest because of its energy efficiency and area efficiency [1,2], providing a promising solution for high-speed architectures. However, the speed superiority of the TD-ADC, enabled by time-domain quantization, has not been sufficiently leveraged due to the long waiting time allocated for multiple bit decisions, which consumes the conversion period [1,2,3]. In addition, the voltage-to-time converter (VTC) front end suffers from linearity degradation at high frequencies ()10GHz) [4]. In this work, we have implemented an asynchronous successive approximation (ASA) timeto-digital converter (TDC), significantly improving the throughputs through time-domain

👥 作者与机构

Qian Chen1, Yuan Liang*1, Chirn Chye Boon1, Qing Liu2

Nanyang Technological University, Singapore, Singapore