A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization

📋 论文概要

该论文提出了一种采用4nm工艺的16Gb/s/pin单端PAM4并行收发器，通过开关抖动补偿和发射机优化解决了PAM4信令中的SNR退化和开关抖动问题，实现了高带宽和高能效的数据传输。

💡 主要创新点

• 提出了一种开关抖动补偿技术，通过调整发射机的时序来减少PAM4信号中的抖动影响。
• 优化了发射机电路设计，包括驱动器和预加重电路，以改善信号完整性和降低功耗。
• 实现了单端PAM4并行收发架构，在4nm工艺下达到了16Gb/s/pin的数据速率。

🏷 关键词

📄 原文摘要

communication, deep learning, advanced driverassistance systems (ADAS), and extended reality (XR), have fueled demand for increased computing power and per-pin interface bandwidth. Recently, four-level pulse-amplitude modulation (PAM4) has been adopted as a solution [1-3]: the throughput is doubled without increasing the baud (Nyquist) rate. Compared to a conventional non-return-tozero (NRZ) signaling, PAM4 requires more design effort: varying from the precise design of I/O circuits to the off-chip characterization. This is in part due to SNR degradation and an increased switching jitter (SWJ). For a 1st-order low-pass filter with a Nyquistfrequency cutoff, SWJ is 35% for the middle eye and 51.2% for the top and bottom eyes

👥 作者与机构

Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim,

Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim Samsung Electronics, Hwaseong, Korea Ever-growing applications, such as 5G