NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin Single-ended Signaling

📋 论文概要

本文介绍了NVLink-C2C，一种支持40Gbps/pin单端信令的片间互连技术，实现了CPU和GPU之间的高带宽、低功耗、低延迟连接，并提供统一的缓存一致性内存地址空间，简化了AI和HPC应用的编程。

💡 主要创新点

• 实现了40Gbps/pin的单端信令片间互连，提供900GB/s的链路带宽
• 通过分层架构（事务层、数据链路层、物理层）实现缓存一致性，统一CPU和GPU内存空间
• 采用接地参考信令（ground referenced signaling）的电气层设计，优化功耗和信号完整性

🏷 关键词

📄 原文摘要

systems, with 900GB/s link between Grace and Hopper, or between two Grace chips. The connection provides a unified, cache-coherent memory address space that combines system and HBM GPU memories for simplified programmability. This coherent, high-bandwidth, lowpower, low latency connection between CPU and GPUs is key to accelerating the most complex AI and HPC workloads. NVLink-C2C uses a layered architecture consisting of transactional layer, data link Layer and physical layer. The physical layer consists of logical and electrical layers. NVLinkC2C electrical layer uses ground referenced signaling (GRS) previously published in [1] and [2] where the primary focus was in-package interconnects, and the speed target [2]

👥 作者与机构

Ying Wei1, Yi Chieh Huang2, Haiming Tang1, Nithya Sankaran1, Ish Chadha1,

Dai Dai1, Olakanmi Oluwole1, Vishnu Balan1, Edward Lee1 Nvidia, Santa Clara, CA Nvidia, Hsinchu, Taiwan 1 2 NVLink-C2C is the enabler for Nvidia’s Grace-Hopper and Grace Superchip