A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 – 41.5TOPS/W for AI Inference

📋 论文概要

本文提出了一款基于28nm工艺的2Mb STT-MRAM存内计算宏，通过改进的位单元设计，解决了标准1T-1MTJ位单元无法满足二值神经网络CIM操作需求的问题，实现了22.4-41.5 TOPS/W的高能效AI推理。

💡 主要创新点

• 提出了一种改进的STT-MRAM位单元，使其能够支持二值神经网络的存内计算操作。
• 设计了完整的28nm 2Mb CIM宏架构，实现了22.4-41.5 TOPS/W的能效，适用于资源受限的边缘AI设备。

🏷 关键词

📄 原文摘要

Emerging non-volatile memory-based computing-in-memory (CIM) is an excellent fit for resource-constrained edge-AI devices [1-6]. MRAM-CIM macros for MAC operations, at present, rely on a crossbar structure or a peripheral circuit modification [2,3]. It remains a great challenge for bottom-up design of MRAM-CIM macro using the standard one transistor - one magnetic tunnel junction (1T-1MTJ) bit-cell: (1) The mainstream spin-transfer-torque (STT) switching mechanism with a standard foundry bit-cell cannot fulfill CIM operation requirements in binary neural networks (BNN). (2) The excessive multi-row/column activation method suffers from a limited read window due to the limited tunnel magnetoresistance ratio and process variation [1,2]. (3) Prior MRAMCIMs rely on analog domain computing, for which an analog-to-digit

👥 作者与机构

Hao Cai1, Zhongjian Bian1, Yaoru Hou1, Yongliang Zhou1, Jia-le Cui1,

Yanan Guo1, Xiaoyun Tian1, Bo Liu1, Xin Si1, Zhen Wang2, Jun Yang1, Weiwei Shan1 Southeast University, Nanjing, China Nanjing Prochip Electronic Technology, Nanjing, China 1 2