A 2×-Interleaved 9b 2.8GS/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input

📋 论文概要

该论文提出了一种2倍交织、9位2.8GS/s、每周期5位的SAR ADC，采用线性化可配置电压-时间（V2T）缓冲器，在3GHz输入下实现>50dB SNDR，解决了多比特SAR ADC中硬件开销大的问题。

💡 主要创新点

• 采用5b/cycle SAR架构，通过增加每周期位数显著提升采样率，同时保持高能效。
• 引入2×交织技术进一步扩展速度，并设计线性化可配置V2T缓冲器改善线性度，降低多比特转换的硬件开销。

🏷 关键词

📄 原文摘要

Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 By increasing the number of bits in each conversion cycle, the sampling rate of SAR ADCs can be considerably extended while maintaining superior energy efficiency. Nevertheless, the hardware cost expands substantially, which in turn limits the speed/bitper-cycle of multi-bit SAR ADCs. Compared with its single bit/cycle counterpart, the multi-bit SAR ADC additionally needs to generate multiple references and conduct multibit comparisons, posing power, timing, and area overheads. Figure 17.1.1 depicts three prior art techniques for producing the multi-reference with different mechanisms. In [1] with a 2b/cycle design, the reference is provided by 2M-1-1 capacitive reference DACs (CDACR) at ΦREF1:N where M and N denote the number of bit conversions per cycle and the number of cycles, respectively. The 1-then-2b/cycle SAR ADC in [2] utilizes 2M-1

👥 作者与机构

Hongzhi Zhao1, Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2

University of Macau, Macao, China