⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一种基于4nm工艺的HBM3 DRAM接口，采用电阻调谐偏移校准和原位裕度检测技术，实现了1.15TB/s的高带宽，解决了高带宽内存接口的瓶颈问题。
Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyogyuem Rhew, Jongshin Shin Samsung Electronics, Hwaseung, Korea A critical performance bottleneck for memory-bound applications such as highperformance computing (HPC), artificial intelligence (AI), and machine learning (ML) applications is the limited memory bandwidth [1]. An HBM3 DRAM interface, based on a WDQS-clocking scheme with high-speed low-voltage-swing terminated logic (LVSTL) I/O, is a promising energy-efficient high-bandwidth solution. The WDQS-clocking scheme is expected to improve the read-valid-window margin (VWM), which is a major limiting factor in achieving DRAM access reliability at high speed. However, the long turn-around read path limits the read VWM improvement. In addition, it is essential to minimize interface area for clustered channel implementations by considering controllers,
Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh,