An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches

📋 论文概要

提出了一种基于单级时间域门控环形振荡器的8位高速ADC，采用2倍插值感测放大器，在5nm CMOS工艺下实现了1.0-1.25GS/s的采样速率和0.7-0.8V的低电源电压，解决了下一代224Gb/s数据通信链路中ADC的能效与速度瓶颈。

💡 主要创新点

• 首次采用单级时间域门控环形振荡器结构实现高速ADC，降低功耗与面积
• 引入2倍插值感测放大器，在不增加量化器数量的情况下提高分辨率
• 在5nm低电压工艺下（0.7-0.8V）实现1.25GS/s采样，适用于高性能DSP系统

🏷 关键词

📄 原文摘要

2 Circuit innovations in medium-low resolution ADCs are among the key enablers to achieving higher data rates, currently at 224Gb/s [1], in the next-generation datacommunication links based on sophisticated DSP techniques. The ADC interleaving factor is defined by the spectral efficiency of the signaling format and the maximum DSP clock rate. At every new generation, the DSP size shrinks thanks to CMOS scaling. However, DSP clock rates are not increasing with new technology nodes. In the 5nm CMOS technology used, the power performance area (PPA) sweet spot for the DSP resides within 0.7-0.8V supply and 1-2GHz clock frequency range. Circuit innovations are necessary for the ADC to benefit from scaling as much as the DSP. The sub-ADC

👥 作者与机构

Abdullah Serdar Yonar1,2, Pier Andrea Francese1, Matthias Brändli1,

Marcel Kossel1, Mridula Prathapan1, Thomas Morf1, Andrea Ruffino1, Taekwang Jang2 IBM Zurich Research Laboratory, Zurich, Switzerland ETH Zürich, Zurich, Switzerland