A 3mW 2.7GS/s 8b Subranging ADC with Multiple-ReferenceEmbedded Comparators

📋 论文概要

本文提出了一种采用多参考嵌入式比较器（Multiple-Reference-Embedded Comparators）的8位2.7GS/s亚采样ADC，仅消耗3mW功率。该设计通过消除传统电阻梯，解决了比较器功耗大、回踢误差和寄生效应严重的问题。

💡 主要创新点

• 提出多参考嵌入式比较器结构，无需电阻梯即可为比较器提供参考电压，显著降低功耗和面积。
• 通过优化比较器设计，减少回踢误差和寄生效应，提升高速下的精度。

🏷 关键词

📄 原文摘要

A subranging ADC is a good choice for wideband applications since the numerous comparators for a flash ADC can be avoided [1-5]. However, despite the reduced number of comparators that a subranging ADC requires, these comparators still consume a considerable amount of power and induce a severe kickback error as well as heavy parasitics, thus degrading the accuracy of the ADC. In addition, a power-hungry resistor ladder is also required to provide reference voltages for the comparators. Although the reference-embedded comparator (REC) can avoid the use of a resistor ladder by realizing a deliberate offset voltage as an embedded reference (ER) voltage inside a comparator [3,5], the aforementioned problems attributed to a number of comparators still exist. Therefore, to retain an ADC with both good power efficiency and good accuracy, a multiple-reference-embedded comparator (MREC) is proposed in this work, which equips

👥 作者与机构

Jia-Ching Wang, Tai-Haur Kuo

National Cheng Kung University, Tainan, Taiwan