A Rail-to-Rail 12MS/s 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting

📋 论文概要

本文提出了一款12MS/s、91.3dB SNDR、94.1dB DR的两步逐次逼近寄存器（SAR）模数转换器（ADC），通过集成的输入缓冲器和预测电平移位技术解决了高分辨率离散时间奈奎斯特ADC驱动困难的问题，实现了轨到轨输入范围和高能效。

💡 主要创新点

• 集成了输入缓冲器，降低了外部驱动要求并提高了功率效率
• 采用预测电平移位技术，实现了轨到轨输入范围内的线性度
• 使用两步SAR架构，在中速下实现了高分辨率和高动态范围

🏷 关键词

📄 原文摘要

utilizing the power-efficient SAR topology at medium speed (1-20MSps) [1-4]. However, highresolution discrete-time Nyquist ADCs are difficult to drive, especially at high sampling frequencies, due to their large input sampling capacitance required to suppress thermal noise. Standalone general-use buffers are costly since a wide supply-range is needed to maintain linearity across signal swing resulting in low power-efficiency. Integrated driving techniques such as [5] have also been explored although the use of the embedded buffer inside the SAR loop requires each SAR decision trial to resettle through the bandwidth of the buffer, while also requiring a separate larger power supply (2.5V) to accommodate the 1.8Vpp signal swing. This work presents the predictive level-shifting integrated driving

👥 作者与机构

Manxin Li1, Calvin Yoji Lee1, Ahmed ElShater1, Yuichi Miyahara2, Kazuki Sobue2,

Koji Tomioka2, Un-Ku Moon1 Oregon State University, Corvallis, OR Asahi Kasei Microdevices, Atsugi, Japan 1 2 Recent years have witnessed the development of high-resolution ADCs >14b