An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees

📋 论文概要

该论文提出了一种利用位稀疏符号幅度乘法与双加法器树的神经引擎，通过采用符号幅度表示替代传统的二进制补码算术，显著降低了乘法能耗，并设计了双加法器树结构以高效处理符号幅度加法，实现了8.09TOPS/W的能效。

💡 主要创新点

• 采用符号幅度乘法替代二进制补码乘法，利用位稀疏性降低乘法能耗35%-67%。
• 设计双加法器树结构，分别处理符号幅度数的符号位和幅度位，避免传统符号幅度加法的高开销。

🏷 关键词

📄 原文摘要

(NNs) continues to increase, spurring the development of high-efficiency neural accelerator engines. Previous neural engines have relied on two’s-complement (2C) arithmetic for their central MAC units (Fig. 29.3.1 top, left). However, gate-level simulations show that sign-magnitude (SM) multiplication is significantly more energy efficient; ranging from 35% (with uniformly distributed operands) to 67% (with normally distributed operands (µ=0, σ=25)). The drawback of sign-magnitude number representation is that SM addition incurs significant overhead in terms of energy consumption and area, requiring upfront comparison of the sign bits and muxing/control to appropriately select between addition and subtraction (Fig. 29.3.1 center, left). This SM addition overhead substantially offsets the gains from SM

👥 作者与机构

Hyochan An, Yu Chen, Zichen Fan, Qirui Zhang, Pierre Abillama, Hun-Seok Kim,

David Blaauw, Dennis Sylvester University of Michigan, Ann Arbor, MI The computational complexity of neural networks