A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration

📋 论文概要

本文提出了一款7位4.5GS/s的4倍时间交织SAR ADC，采用完全片上背景时序偏移校准技术，解决了传统数字校准方法受输入信号限制、收敛时间长和面积大的问题，实现了高能效和鲁棒性。

💡 主要创新点

• 提出了一种完全集成的片上背景时序偏移校准方法，无需外部参考信号，降低了系统复杂度。
• 针对4倍交织架构实现了高效的时序失配检测与校正，支持高速（4.5GS/s）和中等分辨率（7位）操作。

🏷 关键词

📄 原文摘要

With the development of broadband wireless communication and DSP-based wireline communication, there is a rising demand for medium-resolution (6~8bit) ADCs with multi-gigahertz sampling rates and low power consumption. Thus, the time-interleaved SAR ADC is a great choice with high energy efficiency and robust sub-channels. However, costly calibration engines are usually required to resolve channel mismatches, especially timing skew mismatch related to the input signal. Digital detection methods are often limited by the type of input signal, require a long time to converge, and consume area and power. A few analog techniques employ a timing reference signal to simplify the detection mechanisms [1,2]. However, prior art [1] puts the timing reference signal in the same path as the input signal, which complicates its timing and increases subchannel conversion time. In [2] a modulated reference clock injection path on the CDAC

👥 作者与机构

Yi-Hu Wang, Soon-Jyh Chang

National Cheng Kung University, Tainan, Taiwan