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ISSCC 2023Session 7 · SRAM COMPUTE-IN-MEMORYAI / ML28nm CMOS

A 28nm Horizontal-Weight-Shift and Vertical-Feature-ShiftBased Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一种基于水平权重移位和垂直特征移位的分离字线6T-SRAM计算存储单元宏,用于边缘AI设备中的深度可分离卷积操作,解决了传统SRAM CIM对深度可分离卷积支持不足、精度与参数权衡的问题。

💡 主要创新点

工艺节点
28nm CMOS
重要性
发表年份
ISSCC 2023

🏷 关键词

SRAM计算存储深度可分离卷积6T-SRAM边缘AI存内计算

📄 原文摘要

Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang Southeast University, Nanjing, China SRAM-based computation-in-memory (CIM) has shown great potential in improving the energy efficiency of edge-AI devices. Most CIM work [3-4] is targeted at MAC operations with a higher input (IN), weight (W) and output (OUT) precision, which is suitable for standard-convolution layers and fully-connected layers. Edge-AI neural networks tradeoff inference accuracy for network parameters. Depthwise (DW) convolution support is essential for many light-CNN models, such as MobileNet-V2. However, when applying depthwise convolution, recent SRAM CIMs that only support keeping weights inside macro (weight-stationary) face three challenges: (1) decreased energy efficiency due to the short accumulation length (3×3 kernel size) and large DW channel numbers [2-5];

👥 作者与机构

Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren,

分类:AI / ML · 年份:ISSCC 2023