⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种采用正交Doherty架构的数字功率放大器（DPA），在28nm体CMOS工艺下实现了4.1W输出功率和33.6%的峰值功率附加效率（PAE），解决了先进CMOS工艺中低击穿电压和高衬底损耗导致的功率与效率瓶颈问题。
and higher output-power requirements, especially at the base station side. As shown in Fig. 25.1.1, compared to the traditional analog-transmitter architectures with high-power GaAs/GaN poweramplifier (PA) modules, digital transmitters (DTXs) align with Moore’s law to provide compact system size, high system efficiency, and better interface to digital baseband, thus enabling compact and fast system integration as well as a flexible architecture for 5G massive-MIMO applications. However, due to the low supply and breakdown voltages as well as the high substrate loss of advanced CMOS technologies, the design of a highpower high-efficiency digital PA (DPA) is challenging. Besides, 5G communication systems adopt OFDM and high-order QAM modulation techniques for higher data-rates,
Jiaxiang Li1, Yun Yin1, Hang Chen2, Jie Lin1, Yicheng Li1, Xianglong Jia1,
Zhen Hu1, Xiuyin Zhang2, Hongtao Xu1 Fudan University, Shanghai, China South China University of Technology, Guangzhou, China 1 2 5G mobile communication puts forward higher throughputs