JSSC Digital Circuits — ISSCC & JSSC 知识库

JSSC 2025第1期Digital Circuits

A 28 nm 288 TOPS W Attention Based NN Processor With Correlative CIM

28纳米工艺下基于注意力机制的神经网络处理器，支持288 TOPS算力

28nm CMOS, 288 TOPS

JSSC 2025第1期Digital Circuits

A 469 TOPS W Training 234 J Image Inference On Chip Training Accelerator With I

一款高性能芯片训练加速器，支持469 TOPS/W训练和234 J图像推理

469 TOPS/W训练, 234 J图像推理

JSSC 2025第1期Digital Circuits

An Energy Efficient Processor for Real Time Semantic LiDAR SLAM in

一种用于移动机器人实时语义LiDAR SLAM的能效处理器

28nm CMOS, 1.2V, 100MS/s

JSSC 2025第1期Digital Circuits

Energy Efficient Flexible RNS CKKS Processor for FHE Based Privacy Preserving C

一种基于灵活RNS CKKS架构的高效能全同态加密隐私保护处理器。

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JSSC 2025第1期Digital Circuits

Mobile PBR A 28 nm Energy Efficient Rendering Processor for

一款28纳米工艺的高能效渲染处理器，用于实现逼真增强现实效果。

28nm CMOS

JSSC 2025第2期Digital Circuits

DAP A 507 GMACs J 256 Core Domain Adaptive Processor for

一款用于无线通信的507 GMACs、256核域自适应处理器

507 GMACs, 256 Core

JSSC 2025第2期Digital Circuits

PAICORE A 19 Million Neuron 5181 TSOPS W Digital Neuromorphic Processor

PAICORE是一款拥有1900万神经元和5181 TSOPS性能的数字神经形态处理器。

19 Million Neurons, 5181 TSOPS

JSSC 2025第5期Digital Circuits

A 443 mW 624 fps Hyperspectral Image Processor for Spectral Unmixing in MAV Rem

一款用于微型飞行器遥感光谱解混的低功耗高帧率超光谱图像处理器

443 mW, 624 fps

JSSC 2025第5期Digital Circuits

A Real Time Speech Enhancement Processor for Hearing Aids in 28 nm CMOS

一款基于28纳米CMOS工艺的实时语音增强处理器，专为助听器设计。

28nm CMOS, 1.2V

JSSC 2025第5期Digital Circuits

SESOMP A Scalable and Energy Efficient Self Organizing Map Processor for IoT De

一篇关于可扩展且节能的自组织映射处理器在物联网中应用的JSSC论文

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JSSC 2025第6期Digital Circuits

How to Keep Pushing ML Accelerator Performance Know

探讨如何通过理解Rooflines模型持续提升机器学习加速器性能

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JSSC 2025第6期Digital Circuits

PQPU A 44 J Op 694 kOPS Agile Post Quantum Crypto Processor Across

一款支持多种后量子密码算法的44J/694kOPS敏捷处理器

44J/Op, 694kOPS

JSSC 2025第7期Digital Circuits

ANP G A 28 nm 104 pJ SOP Sub mm Asynchronous Hybrid Neural Network

28纳米工艺下104皮焦耳SOP异步混合神经网络嗅觉处理芯片

28nm CMOS, 104pJ SOP

JSSC 2025第7期Digital CircuitsNeural Network Accelerator

An Inductive Loading Simultaneous Noise and Input Matching Technique

该论文提出了一种电感负载同时噪声和输入匹配技术

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JSSC 2025第8期Digital CircuitsNeural Network Accelerator

A 26 G Input Impedance 112 dB Dynamic Range Two Step Direct Conversion

一款具有26G输入阻抗和112dB动态范围的两步直接转换前端设计

26G输入阻抗, 112dB动态范围

JSSC 2025第8期Digital Circuits

A 28 nm Software Defined Accelerator Chip With Circuit Pipeline Scaling and Int

一款28纳米工艺的软件定义加速器芯片，具备电路流水线缩放功能。

28nm CMOS

JSSC 2025第9期Digital CircuitsNeural Network Accelerator

A 255 V Input 100 V Output 862 Peak Efficiency Fibonacci Dickson

一篇关于高效能混合转换器的IEEE JSSC论文

255V Input, 100V Output, 862 Peak Efficiency

JSSC 2025第10期Digital CircuitsNeural Network AcceleratorBiosignal

A 4.6 µW, 133-VPP Common-Mode Interference-Tolerant Biopotential Ampliﬁer for Two-Electrode Recording System in 110-nm CMOS

一种耐受130VPP共模干扰的双电极生物电位放大器

110nm CMOS, 1-1.5V供电, 4.6µW/通道, 130VPP共模耐受

JSSC 2025第10期Digital CircuitsNeural Network AcceleratorBandgap Reference

A Chopping-Free Single-Trim Bandgap Reference Using Amplifier With PTAT Offset Haoyu Zhuang , Yuntao Cao , Shuguang Han, Siyuan Liu, Yizhan Li, Rongqing Sheng , and

提出一种无斩波单修调带隙基准电路，采用PTAT偏移放大器提高精度。

TC 3–8 ppm/°C, 输出噪声1.5 µVrms, 功耗590 µA, 面积0.55 mm²

JSSC 2025第10期Digital Circuits

An 8.62-µW 75-dB DR SoC Fully Integrated SoC for Spoken Language Understanding

一款超低功耗全集成语音理解SoC，具备75dB动态范围和92.9%识别准确率

65nm CMOS, 8.62μW功耗, 2.23mm²面积, 93dB DR(特征提取器), 92.9%准确率

JSSC 2025第10期Digital CircuitsNeural Network Accelerator

Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation Qingzhe Zhang , Student Member , IEEE, Yi Lai, Student Member , IEEE

提出一种Ka波段阻抗不变可变增益移相器，实现高精度相位和幅度控制。

7-bit相位分辨率(360°), 4-bit增益调节(7.5dB动态范围), 0.33°/0.10dB rms误差

JSSC 2025第11期Digital CircuitsNeural Network AcceleratorBiosignal

A 4.6 µW, 133-VPP Common-Mode Interference-Tolerant Biopotential Ampliﬁer for Two-Electrode Recording System in 110-nm CMOS

一种针对两电极系统的生物电位放大器，能耐受130Vpp共模干扰并仅消耗46µW。

110nm CMOS, 1-1.5V供电, 4.6µW/通道, 130Vpp CMI耐受

JSSC 2025第11期Digital CircuitsNeural Network AcceleratorBandgap Reference

A Chopping-Free Single-Trim Bandgap Reference Using Amplifier With PTAT Offset Haoyu Zhuang , Yuntao Cao , Shuguang Han, Siyuan Liu, Yizhan Li, Rongqing Sheng , and

提出一种无需斩波且单次修调的带隙基准电路，利用PTAT偏移放大器提高精度。

3–8 ppm/°C (-55°C~125°C), 1.5 µVrms噪声(0.1–10 Hz), 590 µA电流, 0.55 mm²面积

JSSC 2025第11期Digital Circuits

An 8.62-µW 75-dB DR SoC Fully Integrated SoC for Spoken Language Understanding

一款超低功耗全集成语音理解SoC，具备75dB动态范围和92.9%识别准确率

65nm CMOS, 8.62µW功耗, 2.23mm²面积, 93dB DR, 92.9%准确率

JSSC 2025第11期Digital CircuitsNeural Network Accelerator

Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation Qingzhe Zhang , Student Member , IEEE, Yi Lai, Student Member , IEEE

提出一种Ka波段阻抗不变可变增益移相器，实现高精度相位和幅度控制。

7-bit相位分辨率(360°), 4-bit增益调节(7.5dB动态范围), 0.33°/0.10dB rms误差(移相模式), 0.23°/0.08dB rms误差(VGA模式), 7.4-12.2mW功耗

JSSC 2025第12期Digital CircuitsNeural Network Accelerator

A 14-b Energy-E ﬃcient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source

一种14位能效带宽/功率可调的连续时间ΔΣ调制器，适用于物联网传感器接口。

130nm CMOS, 0.9V, 1MHz采样频率, 85dB峰值SNDR, 46nV/√Hz输入噪声密度

JSSC 2025第12期Digital CircuitsNeural Network Accelerator

A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine VCF Balancing and Frequency Foldback Control for Foldable

双输入双向三电平电池充电器，支持无线电力共享和高效充电。

峰值充电效率96.8%，最大电压转换比92.9%

JSSC 2025第12期Digital CircuitsNeural Network Accelerator

A Trimming-Free 3-in-1 Multi-Mode Passive Switched-Capacitor Ampliﬁer With an Absolute Logarithmic Error of 0.5 dB up to 200

一种无需校准的3合1多模式被动开关电容放大器，具有自动增益控制和对数增益功能。

总增益9.5–85.5 dB，输入参考噪声4.7 µVrms，带宽136 kHz

JSSC 2024第1期Digital Circuits

A 1.5-µW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping

提出了一种28nm CMOS工艺的低功耗关键词检测SoC，采用跳帧RNN算法实现动态功耗优化。

28nm CMOS, 1.48 µW, 92.8% accuracy

JSSC 2024第1期Digital Circuits

C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN

提出一种结合CNN和SNN的互补DNN处理器，实现高效能推理与训练。

85.8 TOPS/W (CIFAR-10), 79.9 TOPS/W (CIFAR-100)

JSSC 2024第1期Digital CircuitsEqualizer

CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States

提出一种基于锁存器的连续时间伊辛机，用于高效解决组合优化问题。

0.656 × 0.680 mm², 40 × 36 自旋阵列

JSSC 2024第1期Digital Circuits

Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and

提出一种支持任意量化的深度学习加速器，具有高效能和多格式数据处理能力。

28nm LP CMOS, 1-8 bit, 30% sparsity, 0.87-5.55 TOPS, 15.1-95.9 TOPS/W

JSSC 2024第2期Digital CircuitsNeural Network AcceleratorBiosignal

A 136-G Input-Impedance Active Electrode for Non-Contact Biopotential

一种136GΩ输入阻抗的有源电极电路，用于非接触式生物电位信号检测。

136GΩ@60Hz, 19.5fF, 700mVpp, 0.72µVrms, 10.46µW@1.2V

JSSC 2024第2期Digital Circuits

New Associate Editor I

Priyanka Raina成为IEEE JSSC新副编辑，专注于特定领域加速器架构与电路研究。

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JSSC 2024第3期Digital CircuitsNeural Network Accelerator

A Li-Ion Battery Input Highly Integrated LED Driver With 96.8% Peak Efficiency and Dual-Color Mixing Capability

一款高效集成的锂离子电池供电LED驱动器，峰值效率达96.8%，支持双色混合调光。

0.18-µm BCD, 2.7–4.2V, 270-550mA, 96.8% peak efficiency

JSSC 2024第3期Digital Circuits

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra

Amber是一款16nm SoC，集成粗粒度可重构阵列，用于加速密集线性代数应用。

538 INT16 GOPS/W, 483 BFloat16 GFLOPS/W

JSSC 2024第3期Digital Circuits

EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning

EPU是首个专为可解释AI设计的硬件加速器，提升系统性能并减少内存占用。

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JSSC 2024第5期Digital Circuits

A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit Jin-O Seo

提出一种具有抗PVT变化模拟数据路径的CNN处理器，实现高能效和低计算误差。

28nm CMOS, 437.9 TOPS/W (模拟数据路径), 44.2 TOPS/W (全系统), ±10%电压变化, -20°C至85°C温度变化下精度损失<0.5%

JSSC 2024第5期Digital CircuitsNeural Network Accelerator

Compact mm-Wave Ultra-Wideband and Low-Noise Phase Alternately Distributed Quasi-Circulators

28nm CMOS工艺下的超宽带低噪声准循环器设计

28nm CMOS, 20.5−35.5 GHz带宽, 4.5 dB TX-to-ANT增益, 3.6 dB ANT-to-RX插入损耗, >21 dB TX-to-RX隔离

JSSC 2024第6期Digital Circuits

A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring Po-Shao Chen

本文提出了一种基于暗通道先验的盲图像去模糊加速器，显著降低了计算延迟和功耗。

40nm CMOS, 0.65V, 65MHz, 28.8mW

JSSC 2024第6期Digital CircuitsNeural Network Accelerator

Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies Hikmet Çeliker , Member , IEEE, Florian

分析比较五种逻辑架构在a-IGZO TFT技术中的性能与适用性。

6英寸玻璃晶圆和柔性基板上的a-IGZO TFT

JSSC 2024第6期Digital Circuits

HGRP: A 181- µW Real-Time Hand Gesture Recognition Processor Based on Bi-Directional Convolution and Iteration-Free

提出一种基于双向卷积的181µW超低功耗实时手势识别处理器。

65nm CMOS, 0.58V, 181µW

JSSC 2024第7期Digital CircuitsNeural Network Accelerator

A 3.8-mW 1.9-m/ √Hz Electrical Impedance Tomography IC With High Input Impedance and Loading Effect Calibration for 3-D Early Breast Cancer

一款低功耗高输入阻抗的3D电阻抗断层成像芯片，提升接触阻抗变化下的稳定性。

3.8mW功耗（不包括注入电流），1.9mΩ/√Hz阻抗分辨率，2.9GΩ@100Hz输入阻抗，230kΩ@1MHz输入阻抗

JSSC 2024第8期Digital Circuits

ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-µJ/Sample On-Chip Learning for Edge-AI Applications

提出一种28nm异步脉冲神经网络处理器，通过优化学习算法降低片上学习能耗。

28nm CMOS, 0.56V, 40MHz, 1.25mm², <0.1µJ/样本学习能耗

JSSC 2024第8期Digital CircuitsNeural Network Accelerator

A 64-Channel Inverter-Based Neural Signal Recording Amplifier With a Novel Differential-Like OTA Achieving an NEF of 0.84 Qiuzhen Xu , Gen Li, Yanyan Liu

提出一种基于逆变器的64通道低功耗低噪声神经信号记录放大器，采用新型差分OTA设计。

NEF 0.84, 每通道平均电流422nA, 每通道面积0.044mm²

JSSC 2024第8期Digital Circuits

FlexSpin: A CMOS Ising Machine With 256 Flexible Spin Processing Elements With 8-b Coefficients for Solving Combinatorial

提出一种256个灵活处理单元的CMOS Ising机器，用于高效解决复杂组合优化问题。

65nm CMOS, 256 PEs, 8-bit coefficients, 28 spin interactions

JSSC 2024第9期Digital Circuits

A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis Ruoyang Liu , Chenhan Wei , Yixiong Yang, Wenxun Wang, Binbin Yuan

提出动态执行神经网络处理器，支持细粒度混合精度训练，提升能效和面积效率。

13.2-TFLOPS/W能效, 1.07-TFLOPS/mm²面积效率

JSSC 2024第9期Digital Circuits

INTIACC: A Programmable Floating- Point Accelerator for Partial Differential Equations Paul

INTIACC是一种可编程浮点加速器，用于高精度求解多种偏微分方程。

65nm CMOS, 1V, 570MHz, 9.12GFLOPS

JSSC 2024第10期Digital CircuitsNeural Network Accelerator

A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses Xiang’ao Qi

一款支持128/256可重构神经元的SNN加速器，实现LIF和IZ神经元模型切换，峰值能效达5.37 TSOPs/W。

峰值能效5.37 TSOPs/W，吞吐量25.6 MSOPs/s，图像特征提取能耗9.27 pJ/pixel

JSSC 2024第10期Digital Circuits

A 73.8k-Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition Tzu-Wei Tong, Tai-Jung Chen , Yi-Yen Hsieh , and Chia-Hsiang Yang

一款用于脑模式识别的低功耗SVM学习加速器，采用CP-SVM算法和硬件优化，显著提升能效。

40nm CMOS, 0.85V, 40MHz, 9.68mW, 73.8k inference/mJ

JSSC 2024第10期Digital Circuits

Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow

Ayaka是一款多功能Transformer加速器，通过低秩估计和异构优化解决计算瓶颈问题。

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JSSC 2024第12期Digital CircuitsNeural Network Accelerator

A 0.00055% THD + N Class-D Audio Amplifier With Capacitive Feedforward PWM and Wide-Band

提出一种采用电容前馈PWM和宽带线性增强技术的D类音频放大器，显著降低失真和噪声。

THD + N 0.00055% (−105.2 dB), FoM THD + N 2119, 静态电流 0.81 mA

JSSC 2023第1期Digital Circuits

A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spooﬁng Fingerprint Authentication Ji-Soo Chang , Eunsang Jang, Y oungkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Uijong Song, Chang-Y eon Cho, Giyeong Ko, Hyunseok Hwang, Junseo Lee, Han-Sol Lee , Y ong-Il Kwon

开发了一种集成指纹传感器前端、高速处理器和安全元件的单芯片生物识别智能卡SoC。

792.5 ms总处理时间（包括防伪指纹认证）

JSSC 2023第1期Digital Circuits

A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10- μm Pitch Interdielet I/O for Runtime Multiprogram Reconﬁguration Sumeet

开发了一种高效能、多程序运行时可重构的通用数字信号处理器（UDSP）。

16-nm, 784-Core

JSSC 2023第1期Digital Circuits

A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for

首款用于癫痫预测的神经信号处理器，集成预处理、特征提取、可重构SVM核和后处理单元，提升预测性能。

92.0%灵敏度, 0.57/h误报率, 8.44ms训练延迟, 2.31mW功耗, 6.05MHz频率

JSSC 2023第1期Digital CircuitsNeural Network Accelerator

A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Uniﬁed Multi-Precision Datapath in 4-nm Flagship Mobile SoC

一款4纳米工艺的多模式8k-MAC神经处理单元，支持多种精度计算并优化硬件利用率。

4.26 TFLOPS/W (FP16), 11.59 TOPS/W (INT8), 1.72 TFLOPS/mm², 3.45 TOPS/mm²

JSSC 2023第1期Digital CircuitsNeural Network Accelerator

A Threshold Implementation-Based Neural Network Accelerator With Power and Electromagnetic Side-Channel Countermeasures

基于阈值实现的神经网络加速器，有效抵御功耗和电磁侧信道攻击。

28nm CMOS, 0.95V, 125MHz

JSSC 2023第1期Digital Circuits

An Energy-Efﬁcient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention Y ang Wang , Y ubin Qin , Dazheng Deng, Jingchuan Wei , Y ang Zhou, Y uanqi Fan, Tianbao Chen, Hao Sun

提出一种能效优化的Transformer处理器，通过动态弱相关性处理降低计算能耗

未明确说明（需查阅完整论文获取具体指标）

JSSC 2023第1期Digital CircuitsProcessor/CPU

Deterministic Frequency and V oltage Enhancements on the POWER10 Processor Brian V anderpool , Phillip J. Restle

POWER10处理器通过数字下垂传感器和核心节流技术提升频率并降低电压。

15%频率提升，10%核心电压降低

JSSC 2023第1期Digital Circuits

RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypt o-Processor for Multiple-Mathematical Problems

RePQC是一款支持多种数学问题的后量子密码处理器，具有高灵活性和能效。

28nm CMOS, 3.4 uJ/Op, 48 kOPS

JSSC 2023第2期Digital Circuits

A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator Hsueh-Y en Shen, Y u-Chi Lee , Tzu-Wei Tong, Student Member , IEEE, and Chia-Hsiang Y ang , Senior Member , IEEE

40纳米工艺下91毫瓦功耗的90帧/秒全高清超分辨率加速器

40nm CMOS, 200MHz, 90fps, 91mW

JSSC 2023第2期Digital Circuits

A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite

提出一种动态精度位串行计算硬件加速器，用于求解偏微分方程

65nm CMOS, 1V, 25.6MHz, 1.59nJ/iteration

JSSC 2023第4期Digital Circuits

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-V ector Scaled 4-bit Quantization in 5 nm

提出一种高效执行Transformer的DNN加速器，采用每向量缩放量化技术，实现高能效推理。

5nm工艺, 0.46V, 95.6 TOPS/W, 0.67V, 1734 inferences/s/W (BERT-Base), 4714 inferences/s/W (ResNet-50)

JSSC 2023第4期Digital Circuits

Non-Linear CNN-Based Read Channel for Hard Disk Drive With 30% Error Rate Reduction and Sequential 200-Mbits/s Throughput in 28-nm CMOS

首款基于CNN的硬盘驱动器读取通道ASIC，错误率降低30.3%

200Mbits/s, 0.86nJ/bit, ~4TOPS/W

JSSC 2023第4期Digital Circuits

Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectiﬁcation

提出超低功耗和小面积模拟音频特征提取芯片，用于关键词识别。

65nm CMOS, 80nW, 0.53mm²

JSSC 2023第6期Digital CircuitsNeural Network Accelerator

A0 . 5 - m/√ Hz Dry-Electrode Bioimpedance Interface With Current Mismatch Cancellation and Input Impedance of 100 M at 50 kHz Qinjing Pan

一种用于干电极生物阻抗监测的高输入阻抗、低噪声传感器接口IC

100 MΩ输入阻抗@50 kHz, 0.5-mV/√Hz灵敏度@1 Hz, 106 dB SNR

JSSC 2023第6期Digital Circuits

An Energy-Efﬁcient Doubl e Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices

首款支持双棘轮协议且具备后向保密性的物联网节能加密处理器

40nm CMOS, 0.56V, 16MHz, 1.03mm², 227k gates, 1.18mW

JSSC 2023第8期Digital Circuits

A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconﬁgurable PE Array Chengshuo Y u

提出一种基于32×32可重构PE阵列的时域波前计算加速器，用于解决最短路径等问题。

65nm CMOS, 776 pJ per task

JSSC 2023第8期Digital Circuits

New Associate Editor I

Ben Keller被任命为IEEE JSSC期刊的新副编辑，专注于数字电路和机器学习加速器研究。

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JSSC 2023第10期Digital CircuitsNeural Network Accelerator

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET

提出一种基于存内计算和高斯随机数生成器的能效贝叶斯神经网络加速器。

32.2 TOP/sW峰值能效, 7.31 GSamp/s随机数生成吞吐量, 1170 GOP/s/W系统能效

JSSC 2023第10期Digital CircuitsNeural Network Accelerator

SNPU: An Energy-Efficient Spike Domain Deep- Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit

提出一种高效能脉冲域深度神经网络处理器SNPU，采用两步编码和全稀疏处理单元提升能效。

输入脉冲编码功耗降低99.4%，操作减少43.5%与71.8%

JSSC 2023第11期Digital Circuits

A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification Tzu-Hsiang Hsu

提出一种0.8V智能视觉传感器，集成微型CNN和可编程传感器内处理电路，用于低功耗边缘设备实时推理。

0.8V, 128×128分辨率, 33.8pJ/pixel·frame, 93.6%准确率

JSSC 2023第11期Digital Circuits

A 47-nW V oice Activity Detector (V AD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-V olatile CAP-ROM

一款基于短时CNN和RNN的低功耗语音活动检测器，采用非易失性电容ROM存储权重。

65nm CMOS, 47nW, 0.022mm², 94%/91% hit rate

JSSC 2023第11期Digital Circuits

An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing

一款用于384通道神经信号处理的在线尖峰排序IC，采用无监督几何感知OSort聚类技术，实现高精度和低功耗。

22nm FDSOI CMOS, 0.0013 mm²/通道, 1.78 µW/通道, 33.9 µs延迟, 97.7%准确率

JSSC 2023第11期Digital Circuits

Design and Characterization of a <4-mW/Qubit 28-nm Cryo-CMOS Integrated Circuit for Full Control of a Superconducting Quantum Processor Unit Cell

设计并表征了一款用于量子计算的28纳米低温CMOS集成电路，实现低功耗高精度量子控制。

28nm CMOS, 4 mW/qubit, 单量子位XY和Z平均门错误率0.17%-0.36%和0.14%-0.17%, 两量子位平均交叉熵基准循环错误率1.2%

JSSC 2022第1期Digital Circuits

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control Katsushige Matsubara , Hanno Lieske , Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa

提出一款12nm工艺的自动驾驶处理器，支持ASIL D安全等级，CNN处理性能达604 TOPS，能效比138 TOPS/W。

12nm工艺, 604 TOPS CNN性能, 138 TOPS/W能效比, 6MB本地内存

JSSC 2022第1期Digital CircuitsNeural Network Accelerator

A 130-dB CMRR Instrumentation Ampliﬁer With Common-Mode Replication

提出一种共模复制技术，实现130dB CMRR和50GΩ输入共模阻抗的仪表放大器。

130dB CMRR, 50GΩ输入共模阻抗, 1.86μA@1.8V, 0.227mm²

JSSC 2022第1期Digital Circuits

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET Colin Schmidt , John Wright , Student Member , IEEE, Zhongkai Wang, Student Member , IEEE, Eric Chang , Albert Ou , Student Member , IEEE

一款采用16nm FinFET工艺的八核144GHz RISC-V向量处理器SoC，集成可编程精度向量加速器。

16nm FinFET, 0.55V, 339MHz, 峰值能效209/92/56 GFLOPs/W (半/单/双精度)

JSSC 2022第2期Digital CircuitsEqualizerNeural Network Accelerator

A 0.4-mA-Quiescent-Current, 0.00091%-THD +N Class-D Audio Ampliﬁer With Low-Complexity Frequency Equalization for PWM-Residual- Aliasing Reduction Yi-Zhi Qiu , Shih-Hsiung Chien

提出一种低复杂度频率均衡技术，降低PWM残留混叠失真，实现低THD+N和低静态电流。

0.00091% THD+N, 0.0027% 最大THD+N, 168kHz fSW, 0.5-µm CMOS

JSSC 2022第2期Digital Circuits

A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling

提出一种基于点云的流水线神经网络处理器，用于移动设备中的3D视觉系统，优化了采样分组层和卷积层的加速。

4.45 ms处理时间，8.24 mm HPE误差，266 mW功耗

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