子分类 · Digital Circuits

Neural Network Accelerator

548 篇相关 JSSC 论文

JSSC 2025第3期RF & WirelessNeural Network Accelerator
A1 . 8 - G Input-Impedance 0.15-μV Input-Referred- Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted
提出一种采用局部正反馈环的斩波放大器，实现高输入阻抗和低输入纹波。
0.18μm CMOS, 5V供电, 1.07mA电流, 1.8GΩ输入阻抗, 0.15μV输入纹波
JSSC 2025第6期MemoryDRAMNeural Network Accelerator
Dual Input Stacked Inverter Based Single Ended DRAM Sense Amplifier Using BL Sw
基于双输入堆叠反相器的单端DRAM感测放大器设计
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JSSC 2025第7期Digital CircuitsNeural Network Accelerator
An Inductive Loading Simultaneous Noise and Input Matching Technique
该论文提出了一种电感负载同时噪声和输入匹配技术
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JSSC 2025第8期Digital CircuitsNeural Network Accelerator
A 26 G Input Impedance 112 dB Dynamic Range Two Step Direct Conversion
一款具有26G输入阻抗和112dB动态范围的两步直接转换前端设计
26G输入阻抗, 112dB动态范围
JSSC 2025第8期RF & WirelessEnergy HarvestingNeural Network Accelerator
A Single Input RF Energy Harvesting Interface With Compensated CEPE Control
一种具有补偿CEPE控制的单输入射频能量收集接口
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JSSC 2025第9期Digital CircuitsNeural Network Accelerator
A 255 V Input 100 V Output 862 Peak Efficiency Fibonacci Dickson
一篇关于高效能混合转换器的IEEE JSSC论文
255V Input, 100V Output, 862 Peak Efficiency
JSSC 2025第9期MemoryNeural Network Accelerator
Digital In Memory Compute for Machine Learning Applications With Input and Mode
该论文提出了一种用于机器学习应用的数字内存计算架构，支持输入和模式切换。
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JSSC 2025第10期RF & WirelessPower AmplifierNeural Network Accelerator
A 200-GHz Modulable Transceiver With 35-dB Tx On–Off Isolation and 16-Gb/s Code Rate for MIMO Radar in 130-nm SiGe Process
一款200GHz可调制收发器芯片组，用于MIMO雷达，具有高隔离度和宽带性能。
170-230GHz频段内35dB隔离度，52GHz饱和功率带宽，10.5dBm最大输出功率
JSSC 2025第10期Digital CircuitsNeural Network AcceleratorBiosignal
A 4.6 µW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS
一种耐受130VPP共模干扰的双电极生物电位放大器
110nm CMOS, 1-1.5V供电, 4.6µW/通道, 130VPP共模耐受
JSSC 2025第10期Digital CircuitsNeural Network AcceleratorBandgap Reference
A Chopping-Free Single-Trim Bandgap Reference Using Amplifier With PTAT Offset Haoyu Zhuang , Yuntao Cao , Shuguang Han, Siyuan Liu, Yizhan Li, Rongqing Sheng , and
提出一种无斩波单修调带隙基准电路，采用PTAT偏移放大器提高精度。
TC 3–8 ppm/°C, 输出噪声1.5 µVrms, 功耗590 µA, 面积0.55 mm²
JSSC 2025第10期Digital CircuitsNeural Network Accelerator
Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation Qingzhe Zhang , Student Member , IEEE, Yi Lai, Student Member , IEEE
提出一种Ka波段阻抗不变可变增益移相器，实现高精度相位和幅度控制。
7-bit相位分辨率(360°), 4-bit增益调节(7.5dB动态范围), 0.33°/0.10dB rms误差
JSSC 2025第11期RF & WirelessPower AmplifierNeural Network Accelerator
A 200-GHz Modulable Transceiver With 35-dB Tx On–Off Isolation and 16-Gb/s Code Rate for MIMO Radar in 130-nm SiGe Process
本文介绍了一种用于MIMO雷达应用的200GHz可调制收发芯片组，具有高隔离度和宽带性能。
3-dB饱和功率带宽52 GHz，最大输出功率10.5 dBm，转换增益24 dB，单边带噪声系数12 dB
JSSC 2025第11期Digital CircuitsNeural Network AcceleratorBiosignal
A 4.6 µW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS
一种针对两电极系统的生物电位放大器，能耐受130Vpp共模干扰并仅消耗46µW。
110nm CMOS, 1-1.5V供电, 4.6µW/通道, 130Vpp CMI耐受
JSSC 2025第11期Digital CircuitsNeural Network AcceleratorBandgap Reference
A Chopping-Free Single-Trim Bandgap Reference Using Amplifier With PTAT Offset Haoyu Zhuang , Yuntao Cao , Shuguang Han, Siyuan Liu, Yizhan Li, Rongqing Sheng , and
提出一种无需斩波且单次修调的带隙基准电路，利用PTAT偏移放大器提高精度。
3–8 ppm/°C (-55°C~125°C), 1.5 µVrms噪声(0.1–10 Hz), 590 µA电流, 0.55 mm²面积
JSSC 2025第11期Digital CircuitsNeural Network Accelerator
Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation Qingzhe Zhang , Student Member , IEEE, Yi Lai, Student Member , IEEE
提出一种Ka波段阻抗不变可变增益移相器，实现高精度相位和幅度控制。
7-bit相位分辨率(360°), 4-bit增益调节(7.5dB动态范围), 0.33°/0.10dB rms误差(移相模式), 0.23°/0.08dB rms误差(VGA模式), 7.4-12.2mW功耗
JSSC 2025第12期RF & WirelessNeural Network Accelerator
A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1–32 GHz in 22-nm FDSOI
一款128-GS/s时间交织子采样ADC前端，支持38GHz输入带宽，用于Ka波段卫星通信。
22nm FDSOI, 12.8GS/s, 38GHz带宽, 39dB SNDR@32GHz, 87mW功耗
JSSC 2025第12期Digital CircuitsNeural Network Accelerator
A 14-b Energy-E fficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source
一种14位能效带宽/功率可调的连续时间ΔΣ调制器，适用于物联网传感器接口。
130nm CMOS, 0.9V, 1MHz采样频率, 85dB峰值SNDR, 46nV/√Hz输入噪声密度
JSSC 2025第12期Power ManagementNeural Network Accelerator
A 1.52-W Capacitor-Drop Sigma-Floating-SC AC/DC Converter for Grid Power to IoT Devices
提出一种基于开关电容的非隔离AC-DC转换器，适用于物联网和智能家居设备。
峰值效率81.3%，最大输出功率1.52W，功率密度739mW/cm³
JSSC 2025第12期Data ConvertersSAR ADCNeural Network Accelerator
A 72-GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3-dB SFDR at 20-GHz /Nyquist Inputs in 16-nm FinFET
本文介绍了一种72-GS/s 9位时间交错流水线-SAR ADC，在20GHz输入下实现55dB SFDR。
72-GS/s, 9-bit, 393.6 mW, 46.4-dB SNDR, 63.6-dB SFDR
JSSC 2025第12期RF & WirelessNeural Network Accelerator
A 77-GHz Hybrid TDM-MIMO Phased-Array Radar With 186-m Detection Range and 3-cm Range Resolution Zitong Zhang
本文提出了一种77GHz混合TDM-MIMO相控阵雷达，采用55nm CMOS工艺，实现了186米探测范围和3厘米角分辨率。
55nm CMOS, 77GHz, 186m探测范围, 3cm角分辨率
JSSC 2025第12期Data ConvertersSAR ADCDAC
A Cryo-CMOS 800-MS /s 7-bit Charge-Injection SAR ADC With Only 4-fF Input Capacitance and 64-dB SFDR in 40-nm Bulk CMOS
一款低温CMOS 800MS/s 7位电荷注入SAR ADC，输入电容仅4fF。
40nm CMOS, 0.84Vpp, 800MS/s, 6.5K, 2.89mW
JSSC 2025第12期Digital CircuitsNeural Network Accelerator
A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine VCF Balancing and Frequency Foldback Control for Foldable
双输入双向三电平电池充电器，支持无线电力共享和高效充电。
峰值充电效率96.8%，最大电压转换比92.9%
JSSC 2025第12期Power ManagementNeural Network Accelerator
A Low-EMI, High-DR Class-D Audio Amplifier With Double-Sided V oltage-Boosting Modulation Jhuang-Wei Cyue
本文提出一种采用双面电压提升调制的数字输入D类音频放大器，具有高动态范围和低电磁干扰。
动态范围121.3 dB，峰值信噪比115 dB，总谐波失真加噪声0.0019%，最大输出功率1.6 W，峰值功率效率87.2%
JSSC 2025第12期Digital CircuitsNeural Network Accelerator
A Trimming-Free 3-in-1 Multi-Mode Passive Switched-Capacitor Amplifier With an Absolute Logarithmic Error of 0.5 dB up to 200
一种无需校准的3合1多模式被动开关电容放大器，具有自动增益控制和对数增益功能。
总增益9.5–85.5 dB，输入参考噪声4.7 µVrms，带宽136 kHz
JSSC 2025第12期RF & WirelessDelta-Sigma ADCNeural Network Accelerator
CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator
提出一种基于Delta-Sigma调制器的无CORDIC数字极坐标发射机架构，提升功率效率和线性度。
65nm CMOS, 33.5%峰值功率附加效率, 24.2-dBm输出功率, 50-MSymbol/s 256-QAM
JSSC 2024第1期MemoryEmerging MemoryNeural Network Accelerator
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices
提出一种基于STT-MRAM的8位精度近存计算宏，采用系统-电路协同设计解决能效和延迟问题。
22nm STT-MRAM, 436GB/s读取带宽, 20ns计算延迟, 53.6-190.2 TOPS/W能效
JSSC 2024第2期Digital CircuitsNeural Network AcceleratorBiosignal
A 136-G Input-Impedance Active Electrode for Non-Contact Biopotential
一种136GΩ输入阻抗的有源电极电路，用于非接触式生物电位信号检测。
136GΩ@60Hz, 19.5fF, 700mVpp, 0.72µVrms, 10.46µW@1.2V
JSSC 2024第2期Power ManagementSAR ADCNeural Network Accelerator
A 15.4-ENOB, Fourth-Order Truncation-Error- Shaping NS-SAR-Nested 16 Modulator With Boosted Input Impedance and Range for
一种高输入阻抗、宽线性输入范围的16调制器，用于生物医学信号采集。
94.5-dB SNDR, 1–500-Hz带宽, 600-mV PP输入, 174.3 dB FoM SNDR, 175.8 dB FoM DR, 208 MΩ@dc输入阻抗
JSSC 2024第2期RF & WirelessCDRPAM-4
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
一款60Gbs PAM-4接收器，采用抖动补偿CDR技术，实现低抖动传输与高带宽容忍。
40nm CMOS, 30-60Gb/s, <-8dB JTRAN, 40MHz JTOL带宽, 60%抖动补偿率
JSSC 2024第2期Power ManagementLDONeural Network Accelerator
A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications
提出一种四相时间开关电容LDO，具有13ns快速响应和低静态电流。
28nm CMOS, 0.45-1V输入, 0.35-0.95V输出, 400mA负载, 3.0fs FoM
JSSC 2024第2期MemorySRAMNeural Network Accelerator
An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications Sheng-Yu Peng
提出了一种适用于传感器边缘应用的SRAM可重构认知计算矩阵，支持多象限乘法和多种激活函数。
0.18-µm CMOS, 3.355 TOPS/W
JSSC 2024第2期Data ConvertersEmerging MemoryNeural Network Accelerator
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip Junjie Wang , Teng Zhang, Shuang Liu , Yihe Liu, Yuancong Wu
设计并实现了一种基于180nm CMOS技术的1Mb RRAM存内计算芯片，采用时间分复用电路和稀疏感知技术，免除了DAC和ADC需求。
180nm CMOS, 13.32 Mb/mm2 (22nm节点归一化), 17.36 TOPS/W (INT4)
JSSC 2024第3期RF & WirelessNeural Network Accelerator
A 14–32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle Performance Enhancement
提出一种新型基于混频器的频率倍增器，通过自调节减少开关四极管占空比，实现宽带高效频率倍增。
1.5V电源电压，6dB转换增益，5.7dBm Psat，17%效率，14-32GHz带宽
JSSC 2024第3期Data ConvertersNeural Network Accelerator
A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS
一款6位1.1GS/s异步电荷注入SAR ADC，具有7GHz ERBW和PVT容差能力。
28nm CMOS, 0.9-1.1V, 1.1GS/s, 35.2dB SNDR, 25.5fJ/conv.-step
JSSC 2024第3期Digital CircuitsNeural Network Accelerator
A Li-Ion Battery Input Highly Integrated LED Driver With 96.8% Peak Efficiency and Dual-Color Mixing Capability
一款高效集成的锂离子电池供电LED驱动器，峰值效率达96.8%，支持双色混合调光。
0.18-µm BCD, 2.7–4.2V, 270-550mA, 96.8% peak efficiency
JSSC 2024第4期Data ConvertersDACNeural Network Accelerator
A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators
一种高效能电平交叉ADC，适用于稀疏信号数字化，采用动态自偏置比较器和新型DAC架构。
65nm CMOS, 64dB SNDR, 20kHz带宽, 1.8fJ/conv.-step
JSSC 2024第4期RF & WirelessPower AmplifierNeural Network Accelerator
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter
提出一种基于1位ΔΣ调制和时间模式调制的数字正交功率放大器，实现高功率回退效率。
65nm CMOS, 2.6GHz, 26.4% PAE@64-QAM 40MSymbol/s, 20.9% PAE@256-QAM 20MSymbol/s
JSSC 2024第4期Power ManagementNeural Network Accelerator
An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-M Input Impedance
提出一种基于变压器优先的离散时间模拟前端，通过输入阻抗提升环路实现超高输入阻抗和低噪声。
389MΩ@1kHz输入阻抗，1.36µVrms输入参考噪声，370nW功耗，NEF=0.34，PEF=0.1
JSSC 2024第4期Power ManagementSAR ADCEnergy Harvesting
An Incremental Step Sensing MPPT Based SI-SIDO Energy Harvester With >99% Peak MPPT Efficiency for an Input Power Range of 30 µW to 33 mW Murali K. Rajendran , Member , IEEE
提出一种基于增量步进传感的MPPT算法，实现高效能量收集系统。
99.5% MPPT效率，88%转换效率，1.8 µW静态功耗
JSSC 2024第4期Power ManagementNeural Network Accelerator
Monolithic 230-V RMS-to-12-VDC AC–DC Converter at 9 mW/mm 2 Enabled by a 31–325-V DC Input Range Capacitive Multi-Ratio DC–DC Converter Tuur
采用180nm高压SOI CMOS工艺实现的全集成230V交流至12V直流转换器，功率密度达9mW/mm²。
180nm SOI CMOS, 230Vrms输入, 12Vdc输出, 9mW/mm²功率密度, 55.1%效率
JSSC 2024第5期Power ManagementBoost ConverterNeural Network Accelerator
A Battery-Input Three-Mode Buck–Boost Hybrid DC–DC Converter With 97.6% Peak Efficiency Shuangxing Zhao
提出一种适用于锂离子电池的三模式非反相升降压混合转换器，峰值效率达97.6%。
0.18-µm CMOS, 3.3-V, 2-MHz, 2.7-4.2V输入, 3.3V输出, 100-800mA
JSSC 2024第5期Power ManagementBuck ConverterNeural Network Accelerator
A High-Efficiency Wide Output Range Reconfigurable Capacitive-Sigma DC–DC Converter
高效可重构电容-Σ DC-DC转换器，峰值效率达98.4%
98.4%峰值效率，1.2V/0.4V输出，2A负载范围
JSSC 2024第5期Digital CircuitsNeural Network Accelerator
Compact mm-Wave Ultra-Wideband and Low-Noise Phase Alternately Distributed Quasi-Circulators
28nm CMOS工艺下的超宽带低噪声准循环器设计
28nm CMOS, 20.5−35.5 GHz带宽, 4.5 dB TX-to-ANT增益, 3.6 dB ANT-to-RX插入损耗, >21 dB TX-to-RX隔离
JSSC 2024第5期RF & WirelessNeural Network Accelerator
RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback Jacob Dean , Student Member , IEEE
本文介绍了一种采用频率转换负反馈的多波段直接下变频接收器。
45nm SOI CMOS, 6-50 GHz, 25-dB增益, 4.1-17-dB噪声系数, 71 mW核心功耗
JSSC 2024第6期RF & WirelessPower AmplifierNeural Network Accelerator
A Dual-Path Transformer-Based Multiband Power Amplifier for mm-Wave 5G
基于双路径变压器的毫米波5G双频段功率放大器设计
28/39 GHz频段饱和输出功率15.3/14.0 dBm，峰值效率34.1%/30.2%
JSSC 2024第6期Digital CircuitsNeural Network Accelerator
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies Hikmet Çeliker , Member , IEEE, Florian
分析比较五种逻辑架构在a-IGZO TFT技术中的性能与适用性。
6英寸玻璃晶圆和柔性基板上的a-IGZO TFT
JSSC 2024第7期Digital CircuitsNeural Network Accelerator
A 3.8-mW 1.9-m/ √Hz Electrical Impedance Tomography IC With High Input Impedance and Loading Effect Calibration for 3-D Early Breast Cancer
一款低功耗高输入阻抗的3D电阻抗断层成像芯片，提升接触阻抗变化下的稳定性。
3.8mW功耗（不包括注入电流），1.9mΩ/√Hz阻抗分辨率，2.9GΩ@100Hz输入阻抗，230kΩ@1MHz输入阻抗
JSSC 2024第7期Data ConvertersSAR ADCNeural Network Accelerator
A 511-µW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique Hao-Hsuan Chang , Ci-Ren Chen , and Tai-Cheng Lee
提出了一种混合两级ADC，结合SAR ADC和ISDM ADC，提升SNDR和功率效率。
370kHz频率，185kHz带宽，511µW功耗，89.3dB SNDR
JSSC 2024第8期RF & WirelessPower AmplifierNeural Network Accelerator
A 13.56-MHz Single-Input Dual-Output Wireless Power and Data Transfer System for Bio-Implants
一种用于生物植入物的13.56MHz单输入双输出无线功率与数据传输系统，采用可重构功率放大器和动态功率分配方案。
423.75 kb/s上行数据速率，6mm距离下62.7%功率传输效率
JSSC 2024第8期Digital CircuitsNeural Network Accelerator
A 64-Channel Inverter-Based Neural Signal Recording Amplifier With a Novel Differential-Like OTA Achieving an NEF of 0.84 Qiuzhen Xu , Gen Li, Yanyan Liu
提出一种基于逆变器的64通道低功耗低噪声神经信号记录放大器，采用新型差分OTA设计。
NEF 0.84, 每通道平均电流422nA, 每通道面积0.044mm²
JSSC 2024第8期RF & WirelessNeural Network Accelerator
A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier With ZVS and Synchronous PFM Control for Wireless Powering Ziyang Luo , Student Member , IEEE
一种高效40.68MHz单级双输出调节整流器，采用ZV开关控制。
65nm CMOS, 2.2V/1.1V双输出, 60.5mW, 90.1%峰值效率
JSSC 2024第9期Power ManagementNeural Network Accelerator
A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC–DC Converter With Inherent Current
提出一种24V输入的高集成交错电感多步降压混合DC-DC转换器，采用新型拓扑和片上栅极驱动方案，实现高效能和小尺寸。
24V输入，1-3.5V输出，峰值效率90.4%，最大负载电流5A，效率82%
JSSC 2024第9期RF & WirelessPAM-4Neural Network Accelerator
A 2 × 56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS
一种基于主动串扰消除的2×56 Gb/s PAM-4接收器，能效达0.78 pJ/b。
56 Gb/s PAM-4, BER <1e-10, 24-dB Nyquist loss, 0.78 pJ/b/lane
JSSC 2024第9期Clocking & PLLsNeural Network Accelerator
An Energy-Efficient Neural Network Accelerator With Improved Resilience Against Fault Attacks
一款具有抗故障攻击能力的能效神经网络加速器ASIC。
高错误检测能力，面积开销5.9%，对NN精度影响可忽略
JSSC 2024第9期Data ConvertersNeural Network AcceleratorBiosignal
Analysis and Design of a 10.4-ENOB 0.92–5.38-µW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications Jonah Van Assche , Student Member , IEEE, and
提出一种新型事件驱动电平交叉ADC，采用自适应时钟方案，显著降低功耗并提升系统兼容性。
8-bit 15-kHz BW, 0.92-5.38 µW
JSSC 2024第10期Digital CircuitsNeural Network Accelerator
A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses Xiang’ao Qi
一款支持128/256可重构神经元的SNN加速器，实现LIF和IZ神经元模型切换，峰值能效达5.37 TSOPs/W。
峰值能效5.37 TSOPs/W，吞吐量25.6 MSOPs/s，图像特征提取能耗9.27 pJ/pixel
JSSC 2024第10期Power ManagementNeural Network Accelerator
A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications
一款全集成九比率开关电容转换器，适用于物联网应用，具有高功率密度和转换效率。
87%峰值效率，最大输出功率421mW，输入电压2.5-5V，输出电压0.1-3.67V
JSSC 2024第12期Digital CircuitsNeural Network Accelerator
A 0.00055% THD + N Class-D Audio Amplifier With Capacitive Feedforward PWM and Wide-Band
提出一种采用电容前馈PWM和宽带线性增强技术的D类音频放大器，显著降低失真和噪声。
THD + N 0.00055% (−105.2 dB), FoM THD + N 2119, 静态电流 0.81 mA
JSSC 2024第12期Data ConvertersTime-Interleaved ADCNeural Network Accelerator
A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized
本文介绍了一种12-GS/s 12位4×时间交织ADC，采用全局抖动注入技术实现输入无关的时序偏差校准。
28nm CMOS, 1.2V, 12-GS/s
JSSC 2024第12期Power ManagementBuck ConverterNeural Network Accelerator
A 12-to-1–1.8-V Hybrid DC–DC Converter With a Charge Converging Phase for Inductor
提出一种带电荷汇聚相的混合降压转换器，显著降低电感电流和传导损耗。
12V输入, 1-1.8V输出, 峰值效率95.4%, DCR 10.5mΩ
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