A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150µA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time

📋 论文概要

本文提出了一种面向先进HBM接口的命令感知混合LDO，通过仅使用20pF片上电容和150μA静态电流实现快速瞬态响应，解决了HBM4中多通道供电噪声和面积限制问题。

💡 主要创新点

• 提出命令感知混合架构，通过预判内存读写命令提前调整LDO工作模式，显著降低瞬态过冲/下冲。
• 采用20pF极小片上电容结合150μA超低静态电流，实现与传统大电容LDO相当的瞬态性能，适合HBM密集集成。

🏷 关键词

📄 原文摘要

KAIST, Daejeon, Korea 3 Kyung Hee University, Yongin, Korea 1 2 *Equally Credited Authors (ECAs) With the advent of the generative AI era, high-bandwidth memory (HBM) has emerged as an irreplaceable solution that can provide ultra-high memory bandwidth (BW) of more than 1TB/s to AI processors. To enable such a high BW, HBM3E accommodates 16 channels (CHs) with two pseudo CHs (pCHs) each, and HBM4 increases them to 32 CHs to double the BW. Each pCH receives a dedicated differential write data strobe (WDQS) from the host. Then, the quadrature clocks (WDQS/2INs) at half frequency are passed to the WDQS buffer, which generates the output clocks, SOUT,Xs (X = I, Q, IB, QB), to sample the DQ data in parallel (top left of Fig. 8.5.1). To ensure error-free sampling for all DQs, low jitter is necessary in the SOUT,Xs, but it is difficult to achieve due to the power-supply-induced jitter (PSIJ) issues

👥 作者与机构

Jaeho Kim*1, Myeongho Han*1, Jooeun Bang1,2, Younghyun Lim3, Jaehyouk Choi1

Seoul National University, Seoul, Korea