A 0.024mm2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration

📋 论文概要

本文提出了一种面积为0.024mm²的全数字分数输出分频器(FOD)，采用基于Split-DTC的背景校准技术，实现了257fs的最差情况抖动。该设计利用单个PLL驱动多个FOD，相比传统多PLL方案显著节省芯片面积和功耗。

💡 主要创新点

• 提出Split-DTC（分片数字时间转换器）架构，实现背景校准，无需额外校准周期，降低面积和功耗。
• 全数字实现，面积仅0.024mm²，适用于SoC多频率时钟生成，克服了模拟方案的面积和功耗瓶颈。
• 通过背景校准抑制DTC非线性，在最差情况下仍保持257fs的低抖动性能。

🏷 关键词

📄 原文摘要

Nanjing, China 1 2 In modern system-on-chips (SoCs), compact, low-jitter and low-power on-chip clock generators are essential for delivering multiple output frequencies to various modules, including microprocessors, IO interfaces, and power-management systems. Conventional clock generators using multiple phase-locked loops (PLLs) often face challenges such as high-power consumption and increased chip area. In contrast, employing multiple fractional output dividers (FODs) driven by a single PLL provides a more compact and power-efficient alternative. FODs can be implemented using either digital-to-time converters (DTCs) [1-3] or digital-to-phase converters (DPCs) [4]. Among these, DTC-based FODs are commonly adopted due to their superior power efficiency and reduced area requirements. However,

👥 作者与机构

Yan Yu1,2, Deng Luo1, Jianjun Chen1, Yang Guo1, Bin Liang1, Yaqing Chi1,

Hanhan Sun1, Jing Xiao2, Hao Gao3, Ming Tao2, Kai Tang2 National University of Defense Technology, Changsha, China Hunan University, Changsha, China 3 Southeast University,