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ISSCC 2025Session 37 · DESIGN-TECHNOLOGY OPTIMIZATION AND DIGITAL ACCELERATORSDigital Circuits

A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6×2.15mm2 SoC and bySPI Chiplets

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📋 论文概要

本文提出了一种可扩展的二维织物上网络(kNOT),通过直接芯片到纱线集成将SoC和bySPI网络芯片嵌入纺织品,支持异构编程、多传感模式和分布式内存,解决了可穿戴电子纺织品在保持柔性和舒适性的同时实现计算和通信的难题。

💡 主要创新点

重要性
发表年份
ISSCC 2025

🏷 关键词

可穿戴计算电子纺织品网络芯片系统级封装分布式内存

📄 原文摘要

Akiyoshi Tanaka1, Fahim Foysal1, Charlie D. Hess1, Will Farrell2, Jim Owens2, Daniel S. Truesdell1, Benton H. Calhoun1 University of Virginia, Charlottesville, VA Nautilus Defense LLC, Pawtucket, RI 1 2 This paper proposes a scalable, 2-dimensional network-on-textiles (kNOT) comprised of systems-on-chip (SoCs) and “bySPI” networking chiplets that are jointly capable of supporting heterogeneous programming, multiple sensing modalities, and a distributed memory system. Emerging e-textiles must retain the flexibility and comfort of their host garment to be viable in wearable applications for healthcare, virtual reality, and sports

👥 作者与机构

Anjali Agrawal1, Zhenghong Chen1, Braden E. Desman1, Jinhua Wang1,

分类:Digital Circuits · 年份:ISSCC 2025