A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction

📋 论文概要

本文提出了一种2nm时钟边沿架构（CEA），用于NPU矩阵乘法单元，通过采用双边缘触发（DET）触发器和时钟门控电路以及自适应时钟占空比控制器，在保持相同性能的同时将时钟频率减半。硅测量结果显示，与传统设计相比，时钟功耗降低约39-40%，总动态功耗降低7-15%，解决了高性能处理器中时钟功耗过大的问题。

💡 主要创新点

• 提出整体时钟边沿架构，利用双边缘触发器实现时钟频率减半而性能不变。
• 设计了双边缘触发的时钟门控电路和自适应时钟占空比控制器，进一步优化功耗。
• 在2nm先进工艺节点上实现并验证了该架构的有效性。

🏷 关键词

📄 原文摘要

Abstract A 2nm clock-edge architecture (CEA) for an NPU matrix-multiplication unit (MXU) features dual-edge-triggered (DET) flip-flops, DET clock-gating circuits, and an adaptive clock dutycycle controller to achieve iso-performance as a conventional (CNV) design while operating at half the clock frequency. Silicon measurements of the CEA MXU demonstrate ~39-40% lower clock power and a total dynamic power reduction of ~7-15%, depending on the workload, as compared to the CNV MXU at iso-throughput. In conventional processors, pipeline registers with single-edge-triggered (SET) flip-flops (FFs) only transition data at one clock edge (e.g., rising edge) with no data movement at the opposite clock edge (e.g., falling edge). Since pipeline data movement only occurs at one clock edge, conventional designs waste half of the dynamic clock power from a microarchitecture perspective. In contrast, dual-edge-triggered (DET) FFs [1]-[17] transition

👥 作者与机构

Yimai Peng1, Daniel Yingling1, Basma Hajri2, Robert Vachon1, Fikre Gebreyohannes2, Vincent Li3, Ghanshyam Chhetri4, Keith Bowman1

Qualcomm, Raleigh, NC, 2Qualcomm, Cork, Ireland, 3Qualcomm, San Diego, CA, 4Qualcomm, Bangalore, India