IBM Telum II Processor Design-Technology Co-Optimizations

📋 论文概要

本文介绍了IBM Telum II处理器的设计-技术协同优化，针对功耗、性能、面积和可靠性（PPAR）进行了全栈改进。该处理器是前代产品的全面升级，通过工艺和设计的联合优化实现了显著的性能提升和能效改善。

💡 主要创新点

• 提出了一种全栈设计-技术协同优化方法，从电路到系统层面同时优化功耗、性能、面积和可靠性。
• 采用了先进的工艺技术和创新的电路设计，如新的时钟分布和电源管理方案，以提升处理器整体效率。
• 通过可靠性增强技术（如冗余和错误校正）在先进工艺节点下维持高可靠性。

🏷 关键词

📄 原文摘要

David Wolpert1, Gerry Strevig2, Chris Berry1, Leon Sigal3, Bill Huott1, Mark Cichanowski2, Matthias Pflanz4, Tobias Werner4, Philipp Salz4, Nick Jing1, Michael Romain1, Iris Leefken4, Richard Serton1, Rajesh Veerabhadraiah5, Dureseti Chidambarrao3, Robert Arelt1, Matt Angyal1, Ben Trombley1, Arvind Haran2, Stefan Hougardy6, Ben Klotz6, Rahul Rao5 IBM, Poughkeepsie, NY IBM, Austin, TX 3 IBM, Yorktown Heights, NY 4 IBM, Böblingen, Germany 5 IBM, Bangalore, India 6 University of Bonn, Bonn, Germany 1 2 The IBM zNext’s Telum II processor [1] is a full-stack overhaul of its predecessor [2], featuring a modified 5nm Samsung bulk technology [3], new IBM-created standard cell and IP libraries, and a variety of further design-technology co-optimizations (DTCO). While die size grew from 530mm² to 600mm² (1.13×), each chip in the dual-chip module became denser, featuring 1.3T shapes (1.25×), 43B transistors (1.38×), and 38km of wire (1.28×)

👥 作者与机构

for Power, Performance, Area, and Reliability