技术领域

Digital Circuits

220 篇相关论文 (2008–2026)

ISSCC 2022 Session 16 Digital Circuits
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS
Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques C. Rudell, Visvesh Sathe
University of Washington, Seattle, WA Ever-increasing global demand for communication bandwidth is incentivizing broader use of the millimeter wave (mm-Wave) frequency band which operates with carrier frequencies exceedi
ISSCC 2022 Session 16 Digital Circuits
A 65nm 63.3µW 15Mbps Transceiver with SwitchedCapacitor Adiabatic Signaling and Combinatorial-PulsePosition Modulation for Body-Worn Video-Sensing AR Nodes
Baibhab Chatterjee, Arunashish Datta, Mayukh Nath, Gaurav Kumar K,
virtual reality (VR) demands 1) high speed (>10Mbps) data transfer among wearable devices around the human body with 2) low transceiver (TRX) power consumption for longer lifetime, especially as communication energy/b is
Nirmoy Modak, Shreyas Sen Purdue University, West Lafayette, IN Recent
ISSCC 2022 Session 16 Digital Circuits
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems
Yuqi Su1, Tony Tae-Hyoung Kim1, Bongjin Kim2
University of California, Santa Barbara, CA 1 2 cycle of operation, the stored spin value is distributed to the four directions based on the lattice graph hardware topology. Note that a spin input can be bypassed to the
Nanyang Technological University, Singapore, Singapore
ISSCC 2022 Session 16 Digital Circuits
Flex6502: A Flexible 8b Microprocessor in 0.8µm MetalOxide Thin-Film Transistor Technology Implemented with a Complete Digital Design Flow Running Complex Assembly Code
Hikmet Çeliker1,2, Antony Sou3, Brian Cobb3, Wim Dehaene1,2, Kris Myny1,2
PragmatIC Semiconductor, Cambridge, United Kingdom 1 3 Integrated circuits based on thin-film transistors (TFTs) are attractive for use in many areas, including the Internet-of-Things (IoT), where ultra-thin circuits on
imec, Leuven, Belgium; 2KU Leuven ESAT, Leuven, Belgium
ISSCC 2022 Session 16 Digital Circuits
A 40nm 60.64TOPS/W ECC-Capable Compute-inMemory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems the sum-of-product error and correct the CIM error. As a result, we pay the penalty of serializing the read operation temporarily. (4) We localize the BL where the sum-ofproduct error has occurred by comparing the CIM result and the correct serial result.
(5) Lastly, victim BLs are tracked with a status register and regularly refreshed to combat, resistance drift and variat
Muya Chang1, Samuel D. Spetalnick1, Brian Crafton1, Win-San Khwa2, Yu-Der Chih3, Meng-Fan Chang2, Arijit Raychowdhury1 In Fig. 16.3.4, we illustrate physical design considerations, power plan, software programmability, a
ISSCC 2022 Session 13 Digital Circuits
A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for
System Performance Scaling, Fast DVFS and Energy, Minimization
Xinjian Liu, Sumanth Kamineni, Jacob Breiholz, Benton H. Calhoun, Shuo Li University of Virginia, Charlottesville, VA A self-powered IoT system-on-chip (SoC) reduces power to sub-µW and employs multiple power-management
ISSCC 2022 Session 13 Digital Circuits
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains
Chi-Hsiang Huang1, Arindam Mandal1, Diego Peña-Colaiocco1,
and wearable applications are aggressively duty-cycled to minimize leakage energy losses. Such systems operate predominantly in Sleep mode, regularly marked by brief intervals of Active operation to perform sensing or co
Edevaldo Pereira Da Silva2, Visvesh Sathe1 University of Washington, S
ISSCC 2022 Session 13 Digital Circuits
A 0.65V 1316µm2 Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving 0.16nJ·%2-Accuracy FoM in 5nm FinFET CMOS
Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin
performance of SoCs, which is rapidly increasing overall chip temperature. As a result, dynamic thermal management (DTM) using a number of temperature sensors is essential. For accurate temperature measurement, the senso
Samsung Electronics, Gyeonggi, Korea Recently, the number of hot spots
ISSCC 2022 Session 13 Digital Circuits
Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor
Brian T. Vanderpool1, Phillip J. Restle2, Eric J. Fluhr3, Gregory S. Still4,
Essex Junction, VT 1 2 Shrinking transistor sizes allow increased logic complexity in modern processors, but smaller dimensions increase power density and require reduced maximum voltage (VDDMAX) for reliability; this ca
Frank Campisano3, Ian Carmichael3, Eric Marz5, Rahul Batra3, Richard W
ISSCC 2022 Session 13 Digital Circuits
Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC
Jae-Gon Lee, Hoyeon Jeon, Younsik Choi, Ahchan Kim
In mobile SoC, clock sources such as PLLs, are expensive resources both in terms of area and power, and they are commonly shared by multiple clock consumers. To that end, the latest SoCs hold tens of PLLs and hundreds of
Samsung Electronics, Hwaseong, Korea
ISSCC 2022 Session 13 Digital Circuits
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency
Rongjin Xu1, Dawei Ye1, Sirou Li1, C. -J. Richard Shi2
University of Washington, Seattle, WA 1 2 The digital injection-locked clock multiplier (ILCM) using ring oscillators (ROs) is a superior choice for clock generation due to its ease of scaling, compact area, and prominen
Fudan University, Shanghai, China
ISSCC 2022 Session 13 Digital Circuits
Clock Generator with ISO26262 ASIL-D Grade Safety Mechanism for SoC Clocking Application
Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An,
advanced integrated circuits for automotive applications have become stricter than at any other time. ISO26262 (Road Vehicle Functional Safety Standard) determines the risk level associated with systematic and random fai
Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin S
ISSCC 2021 Session 35 Digital Circuits
Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm HexagonTM Processor
Vijay Kiran Kalyanam1, Eric Mahurin1, Keith Bowman2, Suresh Venkumahanti1
Qualcomm, Raleigh, NC 1 2 The Hexagon™ compute DSP (CDSP) integrates a master VLIW scalar processor and a slave vector coprocessor to enable high-performance and energy-efficient computing for multimedia, voice, audio, v
Qualcomm, Austin, TX
ISSCC 2021 Session 35 Digital Circuits
A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology
Yasser Moursy1, Thiago Raupp Da Rosa1, Lionel Jure1, Anthony Quelen2,
Sébastien Genevey1, Lionel Pierrefeu1, Emmanuel Grand1, Joerg Winkler3, Jonathan Park4, Gaël Pillonnet2, Vincent Huard1, Andrea Bonzo1, Philippe Flatresse1 Dolphin Design, Meylan, France CEA-Léti, Grenoble, France 3 Glob
ISSCC 2021 Session 35 Digital Circuits
An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC
Bo-Jr Huang, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Rory Huang, Angus Lin,
Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, YS Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang MediaTek, Hs
ISSCC 2021 Session 29 Digital Circuits
115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU
Xiaomin Li1, Yibo Xu1,2, Lizheng Ren1, Weiwei Ge1,2, Jianlong Cai1, Xinning Liu1,2,
applications require ultra-low power consumption. In a conventional design, most modules except the crystal oscillator (XO32), real-time clock (RTC), and retention memory are turned off to reduce the current in sleep sta
Jun Yang1,2 Nanjing Low Power IC Technology Institute, Nanjing, China
ISSCC 2021 Session 29 Digital Circuits
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS
Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe
University of Washington, Seattle, WA Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approaching those o
ISSCC 2021 Session 29 Digital Circuits
A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS
Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, SangHo Kim,
microprocessors for applications such as HPC and AI, the available power is strictly limited by the thermal power budget. To overcome this limitation, recently, each core has been implemented with a dedicated integrated
Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin Samsung Electr
ISSCC 2021 Session 29 Digital Circuits
A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration
Chun-Yu Lin, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin
A compact, low-power, low-jitter clock system supporting multiple output frequencies is required in many applications. Using several PLLs to generate multiple frequencies consumes large power and chip area [1]. Alternati
National Taiwan University, Taipei, Taiwan
ISSCC 2021 Session 29 Digital Circuits
A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur
Qiaochu Zhang1, Shiyu Su1, Cheng-Ru Ho2, Mike Shuo-Wei Chen1
Inphi, Santa Clara, CA 1 2 Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scalingfriendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has bee
University of Southern California, Los Angeles, CA
ISSCC 2021 Session 29 Digital Circuits
80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with SelfReferenced Asynchronous Adaptive Droop Mitigation
Praveen Mosalikanti, Qi Wang, Kuan-Yueh James Shen, Mark Neidengard,
4-to-6.5GHz Frequency Locked Loop (FLL) implemented in 10nm CMOS, targeting high performance SoCs that require uninterrupted, overshoot-free clocks for Dynamic Voltage and Frequency Scaling (DVFS). The FLL supports gradu
Syed Feruz Syed Farooq, Vaughn Grossnickle, Nasser Kurd Intel, Portlan
ISSCC 2021 Session 29 Digital Circuits
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method
Junjie Mu1, Bongjin Kim1,2
now with University of California, Santa Barbara, CA 1 2 Partial differential equations (PDEs) are ubiquitous in physics and engineering and used for understanding various physical phenomena, including heat, diffusion, f
Nanyang Technological University, Singapore, Singapore
ISSCC 2021 Session 29 Digital Circuits
A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Computein-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification
Jong-Hyeok Yoon1, Muya Chang1, Win-San Khwa2, Yu-Der Chih3,
memory-centric workloads (AI, graph-analytics) continue to gain momentum, technology solutions that provide higher on-die memory capacity/bandwidth can provide scalability beyond SRAM. Resistive RAM (RRAM) owing to (1) h
Meng-Fan Chang2, Arijit Raychowdhury1 Georgia Institute of Technology,
ISSCC 2020 Session 31 Digital Circuits
A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators
Tianyu Jia, Yuhao Ju, Jie Gu
Dynamic timing error detection and correction techniques, e.g. razor flops, have been previously applied to microprocessors to exploit the dynamic timing margin within pipelines [1]. Adaptive clock techniques have also b
Northwestern University, Evanston, IL
ISSCC 2020 Session 31 Digital Circuits
A 65nm 8.79TOPS/W 23.82mW Mixed-Signal OscillatorBased NeuroSLAM Accelerator for Applications in Edge Robotics
Jong-Hyeok Yoon, Arijit Raychowdhury
Simultaneous localization and mapping (SLAM) is a quintessential problem in cyber-physical systems with wide-spread applications in mobile robotics, selfdriving vehicles, AR, VR, etc. While computational methods [1] and
Georgia Institute of Technology, Atlanta, GA
ISSCC 2020 Session 25 Digital Circuits
Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for HighPerformance Processors with Wide Voltage-Frequency Operating Range
Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen,
Raghavan Kumar, H. Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De Intel, Hillsboro, OR The clock frequency of high-performance processo
ISSCC 2020 Session 25 Digital Circuits
A Near-Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain UltraLow-Power System-on-a-Chip
Chuxiong Lin1, Weifeng He1, Yanan Sun1, Bingxi Pei1, Zhigang Mao1, Mingoo Seok2
demand a new system-on-a-chip (SoC) that is ultra-low power (mW or even sub-mW level) but highly robust. Such an SoC typically integrates heterogeneous building blocks for supporting a range of features, each ideally ope
Shanghai Jiao Tong University, Shanghai, China Columbia University, Ne
ISSCC 2020 Session 25 Digital Circuits
Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS
Amit Agarwal1, Steven Hsu1, Simeon Realov1, Mark Anders1,
Gregory Chen1, Monodeep Kar1, Raghavan Kumar1, Huseyin Sumbul1, Phil Knag1, Himanshu Kaul1, Sanu Mathew1, Mahesh Kumashikar2, Ram Krishnamurthy1, Vivek De1 Intel, Hillsboro, OR Intel, Bangalore, India 1 2 Flip-flops (FFs
ISSCC 2020 Session 25 Digital Circuits
A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique are generated from the reference frequency, to perform a frequency-shaping SSPD, the associated switch size needs to be minimized to avoid additional spurs at the output.
Hsiu-Hsien Ting, Tai-Cheng Lee, Figure 25.6.3 shows the linear model and open-loop gain comparison. The openloop gain of
These PLLs exhibit features like small area, large tuning range, and multiple output phases. However, their jitter performance is worse than that in LC-oscillator-based PLLs. Although a wider PLL bandwidth can reduce the
National Taiwan University, Taipei, Taiwan Ring-oscillator (RO)-based
ISSCC 2020 Session 25 Digital Circuits
A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS
Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent Carlton
Intel, Hillsboro, OR errors, which are compensated by the DTC-gain-correction loop. Each delay stage uses tristate inverter-based multiplexer (MUX) and switched capacitor banks to realize coarse and fine delays, respecti
ISSCC 2020 Session 25 Digital Circuits
A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing
Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Qiang Li
Power-supply noise (PSN) is a key consideration that determines the performance, as well as functionality of ICs, especially for modern SoCs with significantly increased scale, level of integration, and sophisticated vol
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2020 Session 25 Digital Circuits
A 65nm Edge-Chasing Quantizer-Based Digital LDO Featuring 4.58ps-FoM and Side-Channel-Attack Resistance
Yan He, Kaiyuan Yang
Low-Dropout Regulators (LDOs) are commonly desired for fine-grained power management in SoCs because of their compact area, high current efficiency, and small output ripple. Digital LDOs (DLDOs) are increasingly adopted
Rice University, Houston, TX
ISSCC 2020 Session 25 Digital Circuits
A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector
with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density
intellectual properties (IPs) for better energy efficiency in a system-on-chip design
Jonghyun Oh, Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong Seoul Nati
ISSCC 2020 Session 25 Digital Circuits
A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS
Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi,
regulation for digital IP blocks. A distributed LDO architecture, where a number of dispersed LDO units supply a single domain with shared power delivery network (PDN), has been recently proposed for point-of-load regula
Muhammad Khellah, James Tschanz, Vivek De Intel, Hillsboro, OR Integra
ISSCC 2019 Session 19 Digital Circuits
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput
Zhengyu Chen, Jie Gu
Dynamic time warping (DTW), a variant of the dynamic programming algorithm, is widely used for time series classification [1]. Its strong capability for distance measurement for variable-speed temporal sequences makes DTW
Northwestern University, Evanston, IL
ISSCC 2019 Session 19 Digital Circuits
A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode
David Bol1, Maxime Schramme1, Ludovic Moreau1, Thomas Haine1,
Pengcheng Xu1, Charlotte Frenkel1, Rémi Dekimpe1, François Stas2, Denis Flandre1 UCLouvain, Louvain-la-Neuve, Belgium e-peas semiconductors, Louvain-la-Neuve, Belgium 1 2 Near-threshold circuits operating at ultra-low vo
ISSCC 2019 Session 19 Digital Circuits
Digital Leakage Compensation for a Low-Power and LowJitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology
Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers,
loop (PLL) design [1] continues in the 10nm node and beyond, the leakage from various sources could become an issue in the applications where the reference clock frequency is low and the static phase error is required to
Kuan-Yueh James Shen, Andrey Mezhiba Intel, Hillsboro, OR As the push
ISSCC 2019 Session 19 Digital Circuits
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GeneralPurpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution
Tianyu Jia, Russ Joseph, Jie Gu
Cycle-by-cycle dynamic timing slack (DTS), which represents extra timing margin from the critical-path timing slack reported by the static timing analysis (STA), has been observed at both program level and instruction le
Northwestern University, Evanston, IL
ISSCC 2019 Session 19 Digital Circuits
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors increasing the duty cycle to ~100% and maximizing the time for enabling the high side of the output stage. On the contrary, if FOUT speeds up with respect to FREF due to a large VOUT overshoot event, the duty cycle may reduce to ~0%, minimizing the time the high side of the output stage is enabled.
Francois Atallah1, Keith Bowman1, Hoan Nguyen1, Jihoon Jeong1,
Daniel Yingling1, Yu Sun1, Brad Appel1, Anthony Polomik1, Mahesh Harinath1, Joshua Morelli1, Thomas Moore1, Nathaniel Reeves2, Amer Cassier2, Arijit Raychowdhury3 The TRC oscillator enables the interdependent relationshi
ISSCC 2019 Session 19 Digital Circuits
A 6.4pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio Measurement for EnergyOptimal Operation Across Wide-Range PVT Variation
Jeongsup Lee1, Yiqun Zhang1, Qing Dong1, Wooteak Lim1,
Mehdi Saligane1, Yejoong Kim1, Seokhyeon Jeong1, Jongyup Lim1, Makoto Yasuda2, Satoru Miyoshi3, Masaru Kawaminami2,3, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI Mie Fujitsu Semiconductor Limit
ISSCC 2019 Session 19 Digital Circuits
Computationally Enabled Total Energy Minimization Under Performance Requirements for a VoltageRegulated 0.38-to-0.58V Microprocessor in 65nm CMOS
Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe
University of Washington, Seattle, WA Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage (Vdd) can be set to a Minim
ISSCC 2018 Session 18 Digital Circuits
A High-Efficiency and Fast-Transient Digital-LowDropout Regulator with the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
Jian-He Lin1, Yu-Sheng Ma1, Chia-Ming Huang1, Li-Chi Lin1,
switching-frequency select signal FSEL[1:0]. Initially, the NLSC speeds up the switching frequency, where QBST[6:0] decreases by 1 every 2/3×T1 (=TR/(QN(MAX)-QN(MIN)) time periods. At the end, it slows down the clock fre
Chiao-Hung Cheng1, Ke-Horng Chen1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung
ISSCC 2018 Session 18 Digital Circuits
A Sub-1.55mV-Accuracy 36.9ps-FOM Digital-LowDropout Regulator Employing Switched-Capacitor Resistance
Loai G. Salem, Patrick P. Mercier
Modern DVFS-enabled SoCs require nimble supply regulators that rapidly respond to abrupt load changes and offer fine resolution (e.g., 12.5mV in [1], 10mV in
University of California, San Diego, La Jolla, CA
ISSCC 2018 Session 18 Digital Circuits
A 500mA Analog-Assisted Digital-LDO-Based On-Chip Distributed Power Delivery Grid with Cooperative Regulation and IR-Drop Reduction in 65nm CMOS
Yasu Lu1, Fan Yang2, Feng Chen1, Philip K. T. Mok1
Qualcomm, Singapore 1 2 With the die area of modern processors growing larger and larger, the IR drop across the power supply rail due to its parasitic resistance becomes considerable. There is an urgent demand for local
Hong Kong University of Science and Technology, Hong Kong, China
ISSCC 2018 Session 18 Digital Circuits
A Fully Integrated 40pF Output Capacitor BeatFrequency-Quantizer-Based Digital LDO with Built-In Adaptive Sampling and Active Voltage Positioning
Somnath Kundu1, Muqing Liu1, Richard Wong2, Shi-Jie Wen2, Chris H. Kim1
University of Minnesota, Minneapolis, MN Cisco Systems, San Jose, CA 1 2 Integrated voltage regulators with a wide output current/voltage dynamic range are required to support fast dynamic voltage and frequency scaling (
ISSCC 2018 Session 18 Digital Circuits
A 0.4V 430nA Quiescent Current NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28nm CMOS
Xiaofei Ma1,2, Yan Lu1, Rui P. Martins1,3, Qiang Li2
University of Electronic Science and Technology of China, Chengdu, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal the number of registers. The fine loop contains an 8b SR, controlling eight 1×s
University of Macau, Macau, China
ISSCC 2018 Session 18 Digital Circuits
A 2.5µW 0.0067mm2 Automatic Back-Biasing Compensation Unit Achieving 50% Leakage Reduction in FDSOI 28nm over 0.35-to-1V VDD Range
Anthony Quelen1, Gael Pillonnet1, Philippe Flatresse2, Edith Beigné1
STMicroelectronics, Crolles, France 1 2 Worst-case design and post-silicon tuning are well established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations
CEA-LETI-MINATEC, Grenoble, France,
ISSCC 2018 Session 18 Digital Circuits
A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor
Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li,
Naveen John, Visvesh S. Sathe University of Washington, Seattle, WA Integrated Voltage Regulation (IVR) using buck converters enables efficient, finegrained supply-voltage control in modern SoC domains [1]. However, exis
ISSCC 2018 Session 18 Digital Circuits
Droop Mitigation Using Critical-Path Sensors and an On-Chip Distributed Power Supply Estimation Engine in the z14TM Enterprise Processor
Christos Vezyrtzis1, Thomas Strach2, Pierce I-Jen Chuang1,
Preetham Lobo3, Richard Rizzolo4, Tobias Webel2, Pawel Owczarczyk4, Alper Buyuktosunoglu1, Ramon Bertran1, David Hui4, Susan M. Eickhoff4, Michael Floyd5, Gerard Salem6, Sean Carey4, Stelios G. Tsapepas4, Phillip J. Rest
ISSCC 2017 Session 8 Digital Circuits
A 0.0047mm2 Highly Synthesizable TDC- and DCOLess Fractional-N PLL with a Seamless Lock Range of fREF to 1GHz
Hwasuk Cho1, Kihwan Seong1, Kwang-Hee Choi2, Jin-Hyeok Choi2,
develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several app
Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1 Pohang University of Sci