Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC

📋 论文概要

该论文提出了一种全自动硬件驱动的时钟门控架构，用于5nm Exynos移动SoC，通过完整的时钟覆盖管理未使用时钟网络的切换活动，从而降低功耗。解决了移动SoC中时钟源资源昂贵且利用率低导致的功耗浪费问题。

💡 主要创新点

• 提出全自动硬件驱动的时钟门控架构，无需软件干预，实现动态时钟管理。
• 实现完整的时钟覆盖，确保所有未使用的时钟网络都能被有效门控，最大化功耗节省。
• 针对5nm Exynos移动SoC进行优化，在数十个PLL和数百个MUX/分频器的复杂时钟网络中实现高效门控。

🏷 关键词

📄 原文摘要

In mobile SoC, clock sources such as PLLs, are expensive resources both in terms of area and power, and they are commonly shared by multiple clock consumers. To that end, the latest SoCs hold tens of PLLs and hundreds of MUXes and dividers to provide clocks to thousands of clock consumers spread across the entire die area. Yet mobile computing environments tend to utilize only a small fraction of available circuits at one moment. In that sense, proper management of toggling activity on unused clock nets is considered as one of the key power reduction strategies in the mobile world. This is especially true considering long travel distances required for clock distribution from relatively small number of sources. This new environment asks for different approaches compared to traditional ones [1,2], which are targeted for environments where large volumes of homogeneous circuits are running in parallel. Circuit-level techniques such

👥 作者与机构

Jae-Gon Lee, Hoyeon Jeon, Younsik Choi, Ahchan Kim

Samsung Electronics, Hwaseong, Korea