A 40nm 60.64TOPS/W ECC-Capable Compute-inMemory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems the sum-of-product error and correct the CIM error. As a result, we pay the penalty of serializing the read operation temporarily. (4) We localize the BL where the sum-ofproduct error has occurred by comparing the CIM result and the correct serial result.

📋 论文概要

该论文提出了一种在40nm工艺下集成了RRAM和SRAM的存算一体系统，包含嵌入式Cortex M3微处理器，实现了60.64TOPS/W的高能效，并具备ECC纠错能力。解决了存算一体系统中的可靠性、能效和处理器集成问题。

💡 主要创新点

• 提出混合RRAM/SRAM的存算一体架构，兼顾非易失性和高速缓存。
• 集成ECC纠错机制，提升RRAM存储可靠性。
• 将Cortex M3微处理器置于芯片中心，优化路由拥塞和延迟平衡。

🏷 关键词

📄 原文摘要

Muya Chang1, Samuel D. Spetalnick1, Brian Crafton1, Win-San Khwa2, Yu-Der Chih3, Meng-Fan Chang2, Arijit Raychowdhury1 In Fig. 16.3.4, we illustrate physical design considerations, power plan, software programmability, and the testing procedure. Due to the considerable number of RRAM modules, proper physical design becomes critical in terms of power delivery, balanced delay, and routing congestion. To minimize the routing congestion and balance the delay between the Cortex M3 and all the RRAM modules, placing the microprocessor at the center of the chip turned out to be the best solution. To minimize the IR drop and get the best power delivery, multiple hierarchical power rings/stripes and layers as listed in the table are used. In addition, multiple voltage domains are separated for cleaner power delivery and measuring power consumption for each functional block. To provide a simple and complete platform, a complete application programming interface (API) is

👥 作者与机构

(5) Lastly, victim BLs are tracked with a status register and regularly refreshed to combat, resistance drift and variation.