FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems

📋 论文概要

本文提出FlexSpin，一种可扩展的CMOS Ising机，集成256个灵活自旋处理单元(PE)，通过旁路机制实现任意自旋交互，并利用多自旋每PE和片内缓冲器架构支持大规模扩展，用于高效解决复杂组合优化问题。

💡 主要创新点

• 提出灵活的自旋处理单元，支持任意自旋交互的旁路机制，突破传统晶格拓扑限制。
• 设计可扩展架构，通过多自旋映射每PE和片内缓冲器，实现256 PE的高效集成与级联。

🏷 关键词

📄 原文摘要

University of California, Santa Barbara, CA 1 2 cycle of operation, the stored spin value is distributed to the four directions based on the lattice graph hardware topology. Note that a spin input can be bypassed to the other spins, enabling arbitrary spin interactions. Figure 16.5.2 (bottom) shows a PE layout, which occupies 1321.6µm2. Figure 16.5.3 shows the overall architecture of the implemented FlexSpin Ising machine test chip with 256 PEs. The spin buffers are located at the left and right of the PE array for on-chip scalability based on multiple spins per PE, and the spin I/O transceivers are located at the top and bottom for multi-chip spin operations. Each PE operates one of the four operating modes: (i) spin interaction; (ii) local bias; (iii) random fluctuation; (iv) spin bypass, as illustrated in Fig. 16.5.3 (right). Combinatorial optimization problems (COPs) are ubiquitous in applications such as

👥 作者与机构

Yuqi Su1, Tony Tae-Hyoung Kim1, Bongjin Kim2

Nanyang Technological University, Singapore, Singapore