A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency

📋 论文概要

该论文提出了一种采用注入脉冲整形技术的数字注入锁定时钟乘法器（ILCM），在65nm CMOS工艺下实现了2.5GHz的输出频率和仅0.021mm²的芯片面积。通过解决周期性相位重对齐导致的确定性相位误差，将参考杂散从典型的-50dBc降低至-79dBc。

💡 主要创新点

• 提出注入脉冲整形技术，优化注入时刻的相位对齐精度，有效抑制参考杂散。
• 采用数字校准方法检测并补偿注入定时非理想性，进一步提升杂散性能。

🏷 关键词

📄 原文摘要

University of Washington, Seattle, WA 1 2 The digital injection-locked clock multiplier (ILCM) using ring oscillators (ROs) is a superior choice for clock generation due to its ease of scaling, compact area, and prominent jitter performance. However, the periodic phase realignment in an ILCM can cause a deterministic phase error in the injection moment, which generates an extremely poor reference spur (e.g., -50dBc). Several digital calibration techniques [1-5] have been introduced to reduce the reference spur. The key is to first detect sources of non-idealities (e.g., imperfect injection timing, frequency drift, and slope modulation), and then to enable a specific calibrator to correct each error source. Unfortunately, there are many non-idealities that can affect the injection performance, such as supply ripples, charge injection of the switches, and clock feedthrough, making it impractical to employ multiple

👥 作者与机构

Rongjin Xu1, Dawei Ye1, Sirou Li1, C. -J. Richard Shi2

Fudan University, Shanghai, China