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该论文介绍了POWER10处理器在三星7nm工艺上通过确定性频率提升和电压增强技术来克服尺寸缩小带来的功率密度和可靠性限制。提出了三种技术：工作负载优化频率算法、数字电压降传感器缓解核心逻辑电压降，以及另一种未完整提及的技术，共同提升性能。
Essex Junction, VT 1 2 Shrinking transistor sizes allow increased logic complexity in modern processors, but smaller dimensions increase power density and require reduced maximum voltage (VDDMAX) for reliability; this can severely limit the performance achievable in new technologies. Three techniques increase performance of the POWER10TM processor, built on Samsung 7nm technology, within these constraints: (a) a Workload-Optimized Frequency (WOF) algorithm to maximize frequency within the power envelope, (b) Core Logic Voltage (VDD) droop mitigation using a Digital Droop Sensor (DDS) with core throttling, and (c) Undervolt – a voltage control loop using the DDS to offset loadline uplift and voltage gradients and noise effects to maintain VDD below VDDMAX.
Brian T. Vanderpool1, Phillip J. Restle2, Eric J. Fluhr3, Gregory S. Still4,
Frank Campisano3, Ian Carmichael3, Eric Marz5, Rahul Batra3, Richard Willaman3 IBM, Rochester, MN IBM, Yorktown Heights, NY 3 IBM, Austin, TX 4 IBM, Research Triangle Park, NC 5 IBM