技术领域

Digital Circuits

220 篇相关论文 (2008–2026)

ISSCC 2017 Session 8 Digital Circuits
A 2.5-to-5.75GHz 5mW 0.3psrms-Jitter Cascaded Ring-Based Digital Injection-Locked Clock Multiplier in 65nm CMOS
Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana,
traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter r
Ahmed Elmallah, Pavan Kumar Hanumolu University of Illinois, Urbana, I
ISSCC 2017 Session 8 Digital Circuits
A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO
Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima,
(ILPLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core l
Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, J
ISSCC 2017 Session 8 Digital Circuits
A 2.5ps 0.8-to-3.2GHz Bang-Bang Phase- and Frequency-Detector-Based All-Digital PLL with Noise Self-Adjustment
Taekwang Jang1, Seokhyeon Jeong1, Dongsuk Jeon2, Kyojin David Choo1,
their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, a
Dennis Sylvester1, David Blaauw1 University of Michigan, Ann Arbor, MI
ISSCC 2017 Session 8 Digital Circuits
A 553F2 2-Transistor Amplifier-Based Physically Unclonable Function (PUF) with 1.67% Native Instability
Kaiyuan Yang, Qing Dong, David Blaauw, Dennis Sylvester
Physically Unclonable Functions (PUFs) are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Two types of PUFs exist in literature [1-6]
University of Michigan, Ann Arbor, MI
ISSCC 2017 Session 8 Digital Circuits
8Mb/s 28Mb/mJ Robust True-Random-Number Generator in 65nm CMOS Based on Differential Ring Oscillator with Feedback Resistors
Eunhwan Kim, Minah Lee, Jae-Joon Kim
On-chip true random number generators (TRNG) have been gaining attention as an important component for building secure systems [1]. CMOS TRNGs typically exploit device-level noise, such as thermal or flicker noise to gen
Pohang University of Science and Technology, Pohang, Korea
ISSCC 2017 Session 8 Digital Circuits
Improved Power-Side-Channel-Attack Resistance of an AES-128 Core via a Security-Aware Integrated Buck Voltage Regulator
Monodeep Kar1, Arvind Singh1, Sanu Mathew2, Anand Rajan2, Vivek De2, Saibal Mukhopadhyay1
g. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures to achieve dataindependent supply current
Georgia Institute of Technology, Atlanta, GA Intel, Hillsboro, OR 1 2
ISSCC 2017 Session 20 Digital Circuits
A 13.8µW Binaural Dual-Microphone Digital ANSI S1.11 Filter Bank for Hearing Aids with Zero-ShortCircuit-Current Logic in 65nm CMOS
Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
This paper presents an ANSI S1.11 1/3-octave filter-bank chip for binaural hearing aids with two microphones per ear. Binaural multimicrophone systems significantly suppress noise interference and preserve interaural tim
University of Michigan, Ann Arbor, MI
ISSCC 2017 Session 20 Digital Circuits
A 0.5V-VIN 1.44mA-Class Event-Driven Digital LDO with a Fully Integrated 100pF Output Capacitor
Doyun Kim1, Jonghwan Kim2, Hyunju Ham2, Mingoo Seok1
SK hynix, Icheon, Korea 1 2 In today’s system-on-chip designs, a low-drop-out voltage regulator (LDO) is one of the most popular choices to create a distinct voltage domain owing to its high power density. Many LDOs, how
Columbia University, New York, NY
ISSCC 2017 Session 20 Digital Circuits
A Dual-Symmetrical-Output Switched-Capacitor Converter with Dynamic Power Cells and Minimized Cross Regulation for Application Processors in 28nm CMOS of the regulation loop is much faster than that of power-cell allocation, stability is ensured. Each power cell consists of 2 flying capacitors and 8 power transistors and the VCR can be 2/3× or 1/2×. The configuration of each power cell is optimized to minimize the parasitic loss [6]. The channel selection switches, controlled by sel[n], connect the local output VOL to VO1 or VO2.
Junmin Jiang1,2, Yan Lu1, Wing-Hung Ki2, Seng-Pan U1,3, Rui P. Martins1,4, Figure 20.5.3 shows the control logic that co
and the power-cell shift register. First, the one-shot signals (ck1os and ck2os) control P1 and P2 to charge CC1 and CC2 for one clock period only. The ready signals (ready1 and ready2) are activated after charging is fi
ISSCC 2017 Session 20 Digital Circuits
An Output-Capacitor-Free Analog-Assisted Digital Low-Dropout Regulator with Tri-Loop Control
Mo Huang1,2, Yan Lu1, Seng-Pan U1,3, Rui P. Martins1,4
now with South China University of Technology, Guangzhou, China 2 Synopsys Macau Ltd, Macao, China Instituto Superior Tecnico, Universidade de Lisboa, Portugal 3 4 Low-dropout regulators (LDOs) are widely distributed in
University of Macau, Macau, China
ISSCC 2017 Session 20 Digital Circuits
A 100nA-to-2mA Successive-Approximation Digital LDO with PD Compensation and Sub-LSB Duty Control Achieving a 15.1ns Response Time at 0.5V
Loai G. Salem, Julian Warchall, Patrick P. Mercier
Modern subthreshold SoC designs feature multiple power domains to dynamically track the maximum energy-efficiency point (0.32-0.45V [1]) in response to application demands. While analog low-drop-out (LDO) regulators have
University of California, San Diego, CA
ISSCC 2017 Session 20 Digital Circuits
Digital Low-Dropout Regulator with Anti PVT-Variation Technique for Dynamic Voltage Scaling and Adaptive Voltage Scaling Multicore Processor
Wen-Jie Tsou1, Wen-Hau Yang1, Jian-He Lin1, Hsin Chen1,
processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower po
Ke-Horng Chen1, Chin-Long Wey1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Ye
ISSCC 2017 Session 20 Digital Circuits
A Digitally Controlled Fully Integrated Voltage Regulator with On-Die Solenoid Inductor with Planar Magnetic Core in 14nm Tri-Gate CMOS
Harish Kumar Krishnamurthy, Vaibhav Vaidya, Sheldon Weng,
efficient and widerange local power delivery and management capability with fast transient response for fine-grain DVFS domains of high power density in complex SoCs. Integration of high-quality power inductors that can
Krishnan Ravichandran, Pavan Kumar, Stephen Kim, Rinkle Jain, George M
ISSCC 2016 Session 8 Digital Circuits
iRazor: 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor
Y. Zhang1, M. Khayatzadeh1, K. Yang1, M. Saligane1, N. Pinckney1,
M. Alioto2, D. Blaauw1, D. Sylvester1 University of Michigan, Ann Arbor, MI, National University of Singapore, Singapore, Singapore 1 2 It is well known that technology scaling has led to increasing process/voltage/tempe
ISSCC 2016 Session 8 Digital Circuits
Physically Unclonable Function for Secure Key Generation with a Key Error Rate of 2E-38 in 45nm Smart-Card Chips
Bohdan Karpinskyy, Yongki Lee, Yunhyeok Choi, Yongsoo Kim,
keys or chip IDs based on intrinsic properties of each chip itself [1-2]. PUFs are a step forward to improve the security level compared to traditional NVM (nonvolatile memory) solutions (FUSEs, EEPROM/FLASH, etc.) becau
Mijung Noh, Sanghyun Lee Samsung Electronics, Hwaseong, Korea Physical
ISSCC 2016 Session 8 Digital Circuits
A 6.5-to-23.3fJ/b/mm Balanced ChargeRecycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring
John M. Wilson1, Matthew R. Fojtik1, John W. Poulton1, Xi Chen2,
Stephen G. Tell1, Thomas H. Greer III1, C. Thomas Gray1, William J. Dally2 Nvidia, Durham, NC, 2Nvidia, Santa Clara, CA 1 Signaling over chip-scale global interconnect is consuming a larger fraction of total power in lar
ISSCC 2016 Session 8 Digital Circuits
A 60%-Efficiency 20nW-500μW Tri-Output Fully Integrated Power Management Unit with Environmental Adaptation and Load-Proportional Biasing for IoT Systems
Wanyeong Jung1, Junhua Gu1, Paul D. Myers1, Minseob Shim2,
Seokhyeon Jeong1, Kaiyuan Yang1, Myungjoon Choi1, ZhiYoong Foo1, Suyoung Bang1, Sechang Oh1, Dennis Sylvester1, David Blaauw1 University of Michigan, Ann Arbor, MI, 2Korea University, Seoul, Korea 1 As Internet-of-Things
ISSCC 2016 Session 8 Digital Circuits
Post-Silicon Voltage-Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
Minki Cho, Stephen Kim, Carlos Tokunaga, Charles Augustine,
circuits to lower intrinsic VMIN, retention flops to reduce leakage power during stall periods, and a fully integrated hybrid digital LDO/SCVR regulator to provide a cost-effective means to realize autonomous DVFS under
Jaydeep Kulkarni, Krishnan Ravichandran, James Tschanz, Muhammad Khell
ISSCC 2016 Session 8 Digital Circuits
A 200mA Digital Low-Drop-Out Regulator with Coarse-Fine Dual Loop in Mobile Application Processors
Yong-Jin Lee1,2, Min-Yong Jung1, Shashank Singh2,
Tae-Hwang Kong2, Dae-Yong Kim2, Kwang-Ho Kim2, Sang-Ho Kim2, Jae-Jin Park2, Ho-Jin Park2, Gyu-Hyeong Cho1 KAIST, Daejeon, Korea, Samsung Electronics, Hwaseong, Korea 1 2 A modern mobile application processor (AP) require
ISSCC 2016 Session 8 Digital Circuits
Fully Integrated Low-Drop-Out Regulator Based on Event-Driven PI Control
Doyun Kim, Mingoo Seok
Modern SoC designs employ a number of power domains, many of which are often implemented by low-drop-out (LDO) regulators. The key overhead of the existing LDO design is the large off-chip output capacitor (Cout) for com
Columbia University, New York, NY
ISSCC 2016 Session 8 Digital Circuits
A 4×4×2 Homogeneous Scalable 3D Network-on-Chip Circuit with 326MFlit/s 0.66pJ/b Robust and Fault-Tolerant Asynchronous 3D Links
Pascal Vivet1, Yvain Thonnart1, Romain Lemaire1, Edith Beigne1,
Christian Bernard1, Florian Darve1, Didier Lattard1, Ivan Miro-Panades1, Cristiano Santos1, Fabien Clermidy1, Severine Cheramy1, Frederic Petrot2, Eric Flamand3, Jean Michailos4 CEA-LETI-MINATEC, Grenoble, France, Tima L
ISSCC 2016 Session 19 Digital Circuits
A 0.0021mm2 1.82mW 2.2GHz PLL Using TimeBased Integral Control in 65nm CMOS
Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu,
generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern systems-on-chip (SoCs) require many such PLLs that cater to multi-core proces
Ahmed Elkholy, Seong-Joong Kim, Pavan Kumar Hanumolu University of Ill
ISSCC 2016 Session 19 Digital Circuits
A 65nm CMOS ADPLL with 360μW 1.6ps-INL SS-ADC-Based Period-Detection-Free TDC
Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni,
an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed
Masanori Furuta, Tetsuro Itakura Toshiba, Kawasaki, Japan Several rese
ISSCC 2016 Session 19 Digital Circuits
Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System
Fahim U. Rahman, Visvesh S. Sathe
Clock power remains a substantial contributor to power dissipation, from ultralow-power to high-performance systems [1, 2, 3]. Recently, resonant clocking has been shown to achieve power reduction in clock distribution n
University of Washington, Seattle, WA
ISSCC 2016 Session 19 Digital Circuits
A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation
Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu
Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated togeth
National Taiwan University, Taipei, Taiwan
ISSCC 2016 Session 19 Digital Circuits
A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB Built-In Supply Noise Rejection and Self-Bandwidth Control in 14nm CMOS
Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan,
architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing power budget, a deep sub-mW to low-mW PLL having a FoM between -226dB and -234dB from 0.8GHz to 5GHz is presented. The P
Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser Kurd Intel, Hillsboro,
ISSCC 2016 Session 19 Digital Circuits
A 2.4GHz 1.5mW Digital MDLL Using Pulse-Width Comparator and Double Injection Technique in 28nm CMOS
Hyunik Kim1,2, Yongjo Kim1, Taeik Kim2, Hojin Park2, SeongHwan Cho1
low-jitter clock generator, as it does not suffer much from jitter accumulation [1-4]. By periodically replacing the output edge of the oscillator by a clean edge of the reference, an MDLL has a large effective loop band
KAIST, Daejeon, Korea, Samsung Electronics, Hwaseong, Korea 1 2 A mult
ISSCC 2016 Session 19 Digital Circuits
A 0.2-to-1.45GHz Subsampling Fractional-N AllDigital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection
Somnath Kundu1, Bongjin Kim2, Chris H. Kim1
Multiplying delay-locked loops (MDLLs) are gaining popularity due to their superior noise performance over conventional phase-locked loops (PLLs) [1,2]. Recent designs are trending towards an all-digital implementation t
University of Minnesota, Minneapolis, MN, 2Rambus, Sunnyvale, CA
ISSCC 2016 Session 19 Digital Circuits
A 0.5-to-9.5GHz 1.2µs-Lock-Time Fractional-N DPLL with ±1.25% UI Period Jitter in 16nm CMOS For Dynamic Frequency and Core-Count Scaling in SoC
Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su,
incorporate power management techniques such as dynamic frequency scaling (DFS), which dynamically changes operating frequencies, and dynamic core-count scaling (DCCS), which rapidly power cycles the cores between active
Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori Broadcom, Irvi
ISSCC 2015 Session 8 Digital Circuits
Dual-Use Low-Drop-Out Regulator / Power Gate with Linear and On-Off Conduction Modes for Microprocessor On-Die Supply Voltages in 14nm
Kosta Luria, Joseph Shor, Michael Zelikson, Alex Lyakhov
In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chi
Intel, Yakum, Israel
ISSCC 2015 Session 8 Digital Circuits
Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally Controlled Hybrid LDO/Switched-Capacitor VR with Fast Droop Mitigation
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain,
Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De Intel, Hillsboro, OR A graphics execution core in 22nm improves energy effic
ISSCC 2015 Session 8 Digital Circuits
A 16nm Auto-Calibrating Dynamically Adaptive Clock Distribution for Maximizing Supply-Voltage-Droop Tolerance Across a Wide Operating Range
Keith Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling,
supply voltage (VDD) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previous adaptive circuit techniques aim t
Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, D
ISSCC 2015 Session 8 Digital Circuits
A 0.33V/-40°C Process/Temperature Closed-Loop Compensation SoC Embedding All-Digital Clock Multiplier and DC-DC Converter Exploiting FDSOI 28nm Back-Gate Biasing
Sylvain Clerc1, Mehdi Saligane1,2,3, Fady Abouzeid1, Martin Cochet1,2,
Jean-Marc Daveau1, Cyril Bottoni1, David Bol4, Julien De-Vos4, Dominique Zamora5, Benjamin Coeffic1, Dimitri Soussan1, Damien Croain1, Mehdi Naceur6, Pierre Schamberger6, Philippe Roche1, Dennis Sylvester3 STMicroelectro
ISSCC 2015 Session 8 Digital Circuits
A 10.5μA/MHz at 16MHz Single-Cycle Non-Volatile Memory Access Microcontroller with Full State Retention at 108nA in a 90nm Process
Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale
is an everincreasing demand for lowering power dissipation, especially for sensor nodes, where low energy consumption translates to longer battery life or operation with a smaller/cheaper battery. At the heart of a senso
Kilby Labs, Texas Instruments, Bangalore, India With the Internet of T
ISSCC 2015 Session 8 Digital Circuits
Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic
Wootaek Lim, Inhee Lee, Dennis Sylvester, David Blaauw
Recent low-voltage design techniques have enabled dramatic improvements in miniaturization and lifetime of wireless sensor nodes [1-3]. These systems typically use a secondary battery to provide energy when the sensor is
University of Michigan, Ann Arbor, MI
ISSCC 2015 Session 8 Digital Circuits
An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications
James Myers, Anand Savanth, David Howard, Rohan Gaddh,
Pranay Prabhat, David Flynn ARM, Cambridge, United Kingdom The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses
ISSCC 2014 Session 27 Digital Circuits
A Static Contention-Free Single-Phase-Clocked 24T Flip-Flop in 45nm for Low-Power Applications
Yejoong Kim, Wanyeong Jung, Inhee Lee, Qing Dong,
solution to stagnating energy efficiencies in digital integrated circuits, arising from slowed voltage scaling in nanometer CMOS [1-2]. The design of sequential elements for NTC, as well as in voltage-scaled systems oper
Michael Henry, Dennis Sylvester, David Blaauw University of Michigan,
ISSCC 2014 Session 27 Digital Circuits
A Scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC Decoder for 60GHz Wireless Networks in 28nm UTBB FDSOI
Matthew Weiner1, Milovan Blagojevic1,2,3, Sergey Skotnikov4,
France, 3 EPFL, Lausanne, Switzerland 1 2 Low-density parity-check (LDPC) codes in modern wireless communications are rate- and throughput-scalable, and despite their complexity, decoding them requires low power consumpt
Andreas Burg4, Philippe Flatresse3, Borivoje Nikolic1 University of Ca
ISSCC 2014 Session 27 Digital Circuits
An 821MHz 7.9Gb/s 7.3pJ/b/iteration Charge-Recovery LDPC Decoder
Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
This paper presents a 576b LDPC decoder test-chip designed using a chargerecovery logic family. The chip has been fabricated in a 65nm CMOS process and relies on 16 integrated inductors to achieve energy-efficient operat
University of Michigan, Ann Arbor, MI
ISSCC 2014 Session 27 Digital Circuits
A Multi-Granularity FPGA with Hierarchical Interconnects for Efficient and Flexible Mobile Computing
Cheng C. Wang1, Fang-Li Yuan1, Tsung-Han Yu2, Dejan Markovic1
Following the rapid expansion of mobile computing in the past decade, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy efficiency. An increasi
University of California, Los Angeles, CA, 2Qualcomm, Irvine, CA
ISSCC 2014 Session 27 Digital Circuits
A 0.75-Million-Point Fourier-Transform Chip for Frequency-Sparse Signals
Omid Abari, Ezz Hamed, Haitham Hassanieh, Abhinav Agarwal,
Dina Katabi, Anantha P. Chandrakasan, Vladimir Stojanovic Massachusetts Institute of Technology, Cambridge, MA Applications like spectrum sensing, radar signal processing, and pattern matching by convolving a signal with
ISSCC 2014 Session 27 Digital Circuits
A 210mV 5MHz Variation-Resilient Near-Threshold JPEG Encoder in 40nm CMOS
Nele Reynders, Wim Dehaene
Operating circuits in the near-threshold region enables large energy savings. However, such circuits also pose many challenges, such as increased delay, unwanted leakage paths and high sensitivity to variations. Working
KU Leuven, Leuven, Belgium
ISSCC 2014 Session 27 Digital Circuits
A 6mW 5K-Word Real-Time Speech Recognizer Using WFST Models
Michael Price, James Glass, Anantha P. Chandrakasan
Hardware-accelerated speech recognition is needed to supplement today’s cloud-based systems in power- and bandwidth-constrained scenarios such as wearable electronics. With efficient hardware speech decoders, client devi
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2014 Session 15 Digital Circuits
A 20-to-1000MHz ±14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS
Ahmed Elkholy1, Amr Elshazly2, Saurabh Saxena1,
digital, and mixed-signal functions. They contain a wide variety of modules such as multicore processors, memories, I/O interfaces, power management, and wireless transceivers. Each module has its own unique clock requir
Guanghua Shu1, Pavan Kumar Hanumolu1 University of Illinois, Urbana, I
ISSCC 2014 Session 15 Digital Circuits
A 2.4GHz ADPLL with Digital-Regulated Supply-Noise-Insensitive and Temperature-Self-Compensated Ring DCO
Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang
(RVCOs) ([oscillation frequency change %] / [VDD change %] typically lies in the range from 1 to 2 [1]), an LDO has to provide over 40dB power-supply-rejection ratio (PSRR) to maintain VCO phase noise. However, the volta
MediaTek, Hsinchu, Taiwan Due to the high supply sensitivity of ring v
ISSCC 2014 Session 15 Digital Circuits
A 0.012mm2 3.1mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Frequency Divider
Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin,
recently due to their compatibility with advanced CMOS technology. However, there are two critical factors hindering their uptake in SoC products. One factor is that a digitally controlled oscillator (DCO) is highly sens
Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park Samsung Electronics,
ISSCC 2014 Session 15 Digital Circuits
A 0.0066mm2 780µW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative PhaseCoupled Oscillator Using Edge-Injection Technique
Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon,
digital systems. All-digital PLLs have been proposed to address design issues in conventional analog PLLs. However, current all-digital PLLs require custom circuit design, and therefore cannot fully leverage advanced aut
Satoshi Kondo, Kenichi Okada, Akira Matsuzawa Tokyo Institute of Techn
ISSCC 2013 Session 24 Digital Circuits
Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits
Hiroshi Fuketa1, Masahiro Nomura2, Makoto Takamiya1, Takayasu Sakurai1
37V near-Vt adder array. Fig. 24.9.3(b) shows a block diagram of a test chip. 32 arrays of 32b adders are implemented with input/output latches. The critical path of each adder is 110 FO4 inverter delays. In IRC, static
University of Tokyo, Tokyo, Japan, Semiconductor Technology Academic R
ISSCC 2013 Session 24 Digital Circuits
A 100GB/s Wide I/O with 4096b TSVs Through an Active Silicon Interposer with In-Place Waveform Capturing
Satoshi Takaya1, Makoto Nagata1, Atsushi Sakai2, Takashi Kariya2,
dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications [1-2] and for low-cost high-performance computation [3]. The requirements are extremely low power
Shiro Uchiyama2, Harufumi Kobayashi2, Hiroaki Ikeda2 Kobe University,
ISSCC 2013 Session 24 Digital Circuits
An 8MHz 75μA/MHz Zero-Leakage Non-Volatile Logic-Based Cortex-M0 MCU SoC Exhibiting 100% Digital State Retention at VDD=0V with <400ns Wakeup and Sleep Transitions
Steven C. Bartling, Sudhanshu Khanna, Michael P. Clinton,
Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams Texas Instruments, Dallas, TX We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt,