Digital Circuits

Tobias Gemmeke1, Changmoo Kim2, Jos Hulzink1, Jan Stuyt1, Mookyung Jung2, Jos Huisken1, Soojung Ryu2, Jungwook Kim2, Harmke de Groot1 imec - Holst Centre, Eindhoven, The Netherlands, Samsung Advanced Institute of Technol

ARM, Cambridge, United Kingdom The unrelenting demands of wireless/multimedia DSP workloads necessitate specialized hardware to achieve higher performance and power efficiency. Razor systems offer even greater power effi

Using ultra low-voltage (ULV) is a viable approach towards lowering power consumption. However, due to the narrowing gap between the supply voltage and the threshold voltage, ULV designs inevitably suffer from either low

Bertrand Pelloux-Prayer1, Fabien Giner1, Deepak-Kumar Arora3, Franck Arnaud1, Nicolas Planes1, Julien Le Coz1, Olivier Thomas2, Sylvain Engels1, Giorgio Cesana1, Robin Wilson1, Pascal Urard1 STMicroelectronics, Crolles,

The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signalto-noise ratio (SNR). State-of-the-art channel codes including tu

University of Michigan, Ann Arbor, MI Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These va

sense-amplifier load in the receiver. In this work, IDRV and IPE were set to 95μA and 45μA, respectively. For the receiver equalization, the PMOS diode in the sense-amplifier load is modified to form an active inductor c

spatial temperature distribution, which is essential for dynamic thermal management [1,2]. The number of on-chip temperature sensors in highperformance processors is increasing, with state-of-the-art commercial processor

Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew

dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operat

from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from

This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and

digital TVs and also in other video applications. A low integrated jitter is required for good display quality. However, an extremely low input frequency coming from the horizontal synchronization signal (HSYNC) makes it

include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [12], subharmonically injection-locked techniques [3], and sub-sampli

control gain, KVCO, increases the phase noise contribution arising from the charge pump and loop filter. To resolve this problem, dual-tuning PLLs (DT-PLLs) have been studied [1-4]. The DT-PLL structure adds a narrow-ban

Mobile SoC designs demand a low-power clocking system to maximize battery life. The host PLL is critical since it must remain enabled to support always-on, always-connected operation. In addition, the host PLL should off

synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, m

implemented using digital phase-locked loops (DPLLs), are evolving as the preferred means for synthesizing on-chip clocks. Their main benefits include small area, reduced sensitivity to analog circuit imperfections, and

clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been several approaches to convert analog systems to their digital counterparts

Tatsumi Nakada1, Ken Seki1, Toshiyuki Shimizu1, Naoki Shinjo1, Fumiyoshi Shoji2, Atsuya Uno2, Motoyoshi Kurokawa2 Fujitsu, Kanagawa, Japan RIKEN, Hyogo, Japan 1 2 Many high-performance CPUs employ a multicore architectur

Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Trevor Mudge, Dennis Sylvester, David Blaauw University of Michigan, Ann Arbor, MI Recent high p

Mohammad Hossain1, Moongon Jung1, Ilya Khorosh1, Gokul Kumar1, Young-Joon Lee1, Dean Lewis1, Tzu-Wei Lin1, Chang Liu1, Shreepad Panth1, Mohit Pathak1, Minzhen Ren1, Guanhao Shen1, Taigon Song1, Dong Hyuk Woo1, Xin Zhao1,

IBM Systems and Technology Group, Fishkill, NY 1 2 3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache memory is one

rendering realistic images in high-throughput 3D graphics pipelines. It is the most performance and power-critical operation in programmable vertex and pixel shaders due to the large number of complex floating-point (FP)

blocks of 3D graphics, signal processing and high-performance computing workloads [1,2]. Higher floating-point precisions offer improved accuracy at the expense of performance and energy efficiency, with variable-precisi

an ever increasing number of cores in modern MPSoCs, power reduction and meeting on-chip bandwidth requirements are pressing concerns. Energy efficiency can be increased by percore dynamic voltage and frequency scaling (

maximizing high-performance microprocessor vector datapath utilization in multimedia, graphics, and signal processing workloads [1-3]. A wide SIMD vector permutation engine is required to achieve high-throughput data rea

University of Michigan, Ann Arbor, MI, 2Arizona State University, Tempe, AZ Recently, aggressive voltage scaling was shown as an important technique in achieving highly energy-efficient circuits. Specifically, scaling Vd

University of Freiburg - IMTEK, Freiburg, Germany, HSG-IMIT, Villingen-Schwenningen, Germany Sub-threshold circuits have recently gained attention mainly due to the possibility of operating at the minimum energy per oper

Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques

Alexandre Valentian2, Marc Belleville2, Christine Raynaud1, Damien Croain1, Pascal Urard1 1 STMicroelectronics, Crolles, France, CEA-LETI-MINATEC, Grenoble, France 2 A Low-Density Parity-Check (LDPC) codec circuit is imp

Ronald Nerlich1, Marcus Herzog1, Ralph Ledwa1, Christian Sichert1, Volker Rzehak1, Priya Thanigai2, Bjoern Oliver Eversmann1 1 Texas Instruments, Freising, Germany, Texas Instruments, Dallas, TX 2 In recent years energy-

Filipa Duarte1, Arjan Breeschoten1, Jos Huisken1, Jan Stuyt1, Harmke de Groot1, Francisco Barat2, Johan David2, Johan Van Ginderdeuren2 1 imec - Holst Centre, Eindhoven, The Netherlands, NXP Semiconductors, Leuven, Belgi

high-performance design as it determines the maximum supply voltage, degrading maximum performance and SRAM stability [1]. OBD is an inherently statistical process where some devices fail long before others. Hence, a pri

susceptible to process, voltage, and temperature (PVT) variation. The standard approach for addressing this issue is to increase timing margin at the expense of power and performance. One approach to reclaim these losses

random threshold voltage (Vth) fluctuations is crucial in process optimization and yield learning, particularly for matching critical transistors such as SRAMs, sense amplifiers, differential amplifiers, etc. Traditional

Cypress Semiconductor, San Jose, CA As scaling of silicon CMOS technology continues more challenges emerge in dealing with process variations. In SRAMs process variations directly affect operating margin, subthreshold le

wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, pro

Xeon microprocessors targeting high performance, low-power products [1, 2]. Several key design requirements for this product include high bandwidth, low-latency shared L3 cache access, design modularity to support effici

Joshua Friedrich5, Victor Zyuban2, Ethan Cannon6, A.J. KleinOsowski6 1 IBM Systems and Technology Group, Yorktown Heights, NY IBM Research, Yorktown Heights, NY 3 IBM Systems and Technology Group, Boeblingen, Germany 4 I

Carl Werner, Ken Chang Rambus, Los Altos, CA Clock distribution continues to be a challenging task in digital clocked systems. In a typical clocking architecture (Fig. 9.2.1, top), a phase-locked loop (PLL) produces the

Scaling has accelerated transistor degradation with respect to aging, especially for Negative Bias Temperature Instability (NBTI), which can cause more than a 10% degradation in delay [1]. It is known that in NBTI condit

Tiju Jacob2, Keith Bowman1, Jason Howard1, James Tschanz1, Vasantha Erraguntla2, Nitin Borkar1, Vivek De1, Shekhar Borkar1 1 Intel, Hillsboro, OR Intel, Bangalore, India 2 Many-core processors with on-die network-on-chip

since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference be

IMEC, Leuven, Belgium K.U. Leuven, Leuven, Belgium 2 Digital-intensive PLL architectures emerge [1]-[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz12GHz synthesi

State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1-3], of

spurs [1], [2]. However, the actual results depend dramatically on the linearity of the time-to-digital converter (TDC). This paper presents a 3MHz bandwidth fractional-N synthesizer, which combines a 4ps TDC with digita

University of Twente, Enschede, Netherlands National Semiconductor, Santa Clara, CA 2 In PLL designs, a wide loop bandwidth is often desired as it offers fast settling time, reduces on-chip loop filter area and sensitivi

Atheros Communications, Santa Clara, CA Digital Phase-Locked Loops (DPLLs), which are amenable to CMOS process scaling, have recently been demonstrated for both wireless and wireline applications as alternatives to conve

NEC, Kawasaki, Japan NEC Electronics, Kawasaki, Japan 2 All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operatio