技术领域

Digital Circuits

220 篇相关论文 (2008–2026)

ISSCC 2010 Session 26 Digital Circuits
A 3.5GHz Wideband ADPLL with Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation
Colin Weltin-Wu1,2, Enrico Temporiti3, Daniele Baldi3, Marco Cusmai2,
Columbia University, New York, NY University of Pavia, Pavia, Italy 3 STMicroelectronics, Pavia, Italy 2 The digital-intensive approach to frequency synthesis embodied by the ADPLL
Francesco Svelto2
ISSCC 2009 Session 14 Digital Circuits
A 300mV 494GOPS/W Reconfigurable Dual-Supply 4Way SIMD Vector Processing Accelerator in 45nm CMOS
Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven K. Hsu,
Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar Intel, Hillsboro, OR High-throughput parallel SIMD vector computations are the most performance and power-critical operations in multimedia, graphics and signal processi
ISSCC 2009 Session 14 Digital Circuits
A 1GHz Digital Channel Multiplexer for Satellite Outdoor Unit Based on a 65nm CMOS Transceiver
P. Busson1, N. Chawla2, J. Bach1, S. Le Tual1, H. Singh2, V. Gupta2, P. Urard1
level and characterized for different input signal slopes, load capacitances, and process corner conditions. The extracted timing characteristics have been used as constraint to drive the digital block implementation. Ba
STMicroelectronics, Crolles, France STMicroelectronics, Noida, India i
ISSCC 2009 Session 14 Digital Circuits
A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO Detector
Mahdi Shabany, P. Glenn Gulak
The high spectral efficiency offered by multiple-input-multiple-output (MIMO) technology has made it the technology-of-choice in many standards like IEEE 802.16e/m (WiMAX) and the long term evolution (LTE) project and em
University of Toronto, Toronto, Canada
ISSCC 2009 Session 14 Digital Circuits
A 110nm RFCMOS GPS SoC with 34mW -165dBm Tracking Sensitivity
J-M Wei1, C-N Chen1, K-T Chen1, C-F Kuo1, B-H Ong2, C-H Lu1, C-C Liu1,
H-C Chiou1, H-C Yeh1, J-H Shieh1, K-S Huang1, K-I Li1, M-J Wu2, M-H Li1, S-H Chou1, S-L Chew2, W-L Lien2, W-G Yau1, W-Z Ge1, W-C Lai1, W-H Ting1, Y-J Tsai1, Y-C Yen1, Y-C Yeh1 1 2 MediaTek, Hsinchu, Taiwan MediaTek, Sing
ISSCC 2009 Session 14 Digital Circuits
A 0.55V 16Mb/s 1.6mW Non-Coherent IR-UWB Digital Baseband with ±1ns Synchronization Accuracy
Patrick P. Mercier, Manish Bhardwaj, Denis C. Daly, Anantha P. Chandrakasan
sensing applications, in part because they can be easily duty-cycled to achieve extreme energy efficiency. Within pulsed radios, non-coherent (NC) RF front ends that use simple square-and-integrate samplers offer signifi
Massachusetts Institute of Technology, Cambridge, MA IR-UWB radios are
ISSCC 2008 Session 28 Digital Circuits
A 9.5GHz 6ps-Skew Space-Filling-Curve Clock Distribution with 1.8V Full-Swing Standing-Wave Oscillators Mamoru Sasaki
Hiroshima University, Hiroshima Japan, Global clock distribution is becoming increasingly difficult for
multi-GHz microprocessors because the skew and jitter are proportional to the large latency in the conventional tree structure. A number of resonant techniques have been reported to overcome clock distribution problems [
ISSCC 2008 Session 28 Digital Circuits
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS
A. V. Rylyakov1, J. A. Tierno1, D. Z. Turker2, J.-O. Plouchart1,
H. A. Ainspan1, D. Friedman1 1 IBM T.J. Watson, Yorktown Heights, NY Texas A&M University, College Station, TX 2 Digital phase-lock loop (DPLL) design approaches offer multiple advantages, including compactness, broad pr
ISSCC 2008 Session 28 Digital Circuits
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation
Keng-Jan Hsiao, Tai-Cheng Lee
A conventional DLL employs a phase detector (PD), a charge pump, and a loop filter to compare and adjust the phase difference between the reference clock and the delayed clock. Ideally, when the DLL is locked, the delay
National Taiwan University, Taipei, Taiwan
ISSCC 2008 Session 28 Digital Circuits
A Resonant Global Clock Distribution for the Cell Broadband-EngineTM Processor
Steven Chan1, Phillip Restle1, Thomas Bucelot1, Stephen Weitzel2,
Junction, VT which results in a good balance between voltage ripple (affects power savings and skew/jitter improvement) and time to reach steady state (affects startup and low-frequency operation). The purpose of the fri
John Keaty2, John Liberty2, Brian Flachs2, Richard Volant3, Peter Kapu
ISSCC 2008 Session 28 Digital Circuits
A 45nm 4Gb 3-Dimensional Double-Stacked MultiLevel NAND Flash Memory with Shared Bitline Structure
Ki-Tae Park, Doogon Kim, Soonwook Hwang, Myounggon Kang,
Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jaehoon Jang, Han-Soo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim and Won-Seong Lee Samsung, Hwasung, Korea Recently, 3-dimensional (3-D) memories have regained attention
ISSCC 2008 Session 28 Digital Circuits
An 8kB EEPROM-Emulation DataFLASH Module for Automotive MCU m2, WSM judges it as the degradation of erase time and sets the erase time degradation detect bit in the status register.
Shinji Kawai, Akira Hosogane, Shigehiro Kuge, Toshihiro Abe,
Kohei Hashimoto, Tsukasa Oishi, Naoki Tsuji, Kiyohiko Sakakibara, Kenji Noguchi Figure 28.2.5 shows a software-leveling scheme with background operation (BGO) between a 512kB code Flash (with 50MHz highspeed page read mo
ISSCC 2008 Session 28 Digital Circuits
A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate
Yan Li1, Seungpil Lee1, Yupin Fong1, Feng Pan1, Tien-Chien Kuo1, Jong Park1,
Tapan Samaddar1, Hao Nguyen1, Man Mui1, Khin Htoo1, Teruhiko Kamei1, Masaaki Higashitani1, Emilio Yero1, Gyuwan Kwon1, Phil Kliza1, Jun Wan1, Tetsuya Kaneko2, Hiroshi Maejima2, Hitoshi Shiga2, Makoto Hamada2, Norihiro Fu
ISSCC 2008 Session 16 Digital Circuits
A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter 256 to improve speed and read reliability; devices in the readbuffer are lengthened to achieve higher speed and lower read current variability in sub-Vt.
Joyce Kwong1, Yogesh Ramadass1, Naveen Verma1, Markus Koesler2,
Korbinian Huber2, Hans Moormann2, Anantha Chandrakasan1 A custom timing closure approach was developed to account for increased delay variability in sub-Vt. As shown in Fig. 16.7.3, delay distributions of timing paths in
ISSCC 2008 Session 16 Digital Circuits
A 320mV 56µW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS
Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu,
the most performance and power-critical operation in video encoding applications, where a wide range of throughput and power constraints are required to handle a variety of video resolution, frame rate and application sp
Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar Intel, Hillsboro, OR M
ISSCC 2008 Session 16 Digital Circuits
A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip
Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu,
has been adopted as the major coding standard in recently popular high definition video due to its excellent coding efficiency. Several implementations have been developed [1-3], but, their performance is limited to base
Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang National Chiao-Tung
ISSCC 2008 Session 16 Digital Circuits
A 512GOPS Fully-Programmable Digital Image Processor with full HD 1080p Processing Capabilities
Sumito Arakawa, Yuji Yamaguchi, Satoshi Akui, Yasushi Fukuda,
Hirofumi Sumi, Hiroshi Hayashi, Masahiro Igarashi, Kei Ito, Hidetoshi Nagano, Masatoshi Imai, Naosuke Asari Sony, Tokyo, Japan The introduction of high-resolution CMOS image sensors [1] has encouraged the development of
ISSCC 2008 Session 16 Digital Circuits
A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling SatelliteTransmission Portable Devices
P. Urard1, L. Paumier2, V. Heinrich1, N. Raina3, N. Chawla3, 1
Services compliant 2nd Generation Satellite Digital Video Broadcast (DVB-S2) [1] codec is presented. Previously published silicon implementations respecting this stringent standard reports power consumption between 800mW
STMicroelectronics, Crolles, France, 2STMicroelectronics, Grenoble, Fr
ISSCC 2008 Session 16 Digital Circuits
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired VisualAttention Engine
Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim,
reduce the complexity of object recognition by decreasing the amount of image data to be processed. As Fig. 16.2.1 illustrates, salient parts of a scene are roughly selected by the visual attention mechanism in advance s
Donghyun Kim, Jeong-Ho Woo, Hoi-Jun Yoo KAIST, Daejeon, Korea The visu
ISSCC 2008 Session 16 Digital Circuits
iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor
Chih-Chi Cheng1, Chia-Hua Lin1, Chung-Te Li1, Samuel Chang1,
in surveillance, healthcare, intelligent vehicle control, human-machine interfaces, etc. Hardware solutions exist for video analysis. Analog on-sensor processing solutions [1] feature image sensor integration. However, t
Chia-Jung Hsu2, Liang-Gee Chen1 1 National Taiwan University, Taipei,