A Source-Synchronous 90Gb/s Capacitively Driven Serial On-Chip Link Over 6mm in 65nm CMOS

📋 论文概要

该论文提出了一种基于电容驱动的源同步串行片上链路，解决了多核MPSoC中全局通信的高带宽、低功耗和同步问题。在65nm CMOS工艺上实现了90Gb/s的数据传输速率，传输距离达6mm。

💡 主要创新点

• 采用电容耦合驱动技术替代传统的RC延迟限制的长线驱动，降低功耗并提高速度。
• 实现源同步架构，避免全局高速时钟分布，适用于GALS系统。
• 串行化传输方式减少互连线数量，同时利用电容耦合实现高带宽密度。

🏷 关键词

📄 原文摘要

an ever increasing number of cores in modern MPSoCs, power reduction and meeting on-chip bandwidth requirements are pressing concerns. Energy efficiency can be increased by percore dynamic voltage and frequency scaling (DVFS) and by employing a globally-asynchronous, locally-synchronous (GALS) system architecture in which distribution of a synchronous high-speed clock is not required. For global on-chip communication this presents major challenges due to the need for reliable data synchronization, high bandwidth requirements and speed limiting RC effects on long wires. It has been shown recently that low-swing differential on-chip links provide highest bandwidth, low energy-per-bit and uninterrupted transfers over

👥 作者与机构

Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth,

Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter, Gerhard Fettweis Technical University Dresden, Dresden, Germany While continued scaling of feature sizes allows for