A 0.004mm2 250µW ΔΣ TDC with Time-Difference Accumulator and a 0.012mm2 2.5mW Bang-Bang Digital PLL Using PRNG for Low-Power SoC Applications

📋 论文概要

本文提出了一种高分辨率、低功耗的ΔΣ时间数字转换器（TDC）和Bang-Bang数字锁相环（PLL）。TDC采用时间差累加器实现0.004mm²面积和250µW功耗，PLL使用伪随机数发生器（PRNG）以2.5mW功耗实现0.012mm²面积，解决传统TDC功耗高和模拟电路复杂的问题。

💡 主要创新点

• 提出时间差累加器（Time-Difference Accumulator）技术，实现小面积低功耗的ΔΣ TDC。
• 在Bang-Bang数字PLL中引入伪随机数发生器（PRNG），降低带内噪声或抖动。
• 整体电路面积显著减小（TDC仅0.004mm²，PLL仅0.012mm²），适合集成。

🏷 关键词

📄 原文摘要

clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been several approaches to convert analog systems to their digital counterparts and a highresolution time-to-digital converter (TDC) is a key element for the digitalization of analog circuits (Fig. 14.1.1). Recently, TDCs using a noise shaping technique with oversampling have been introduced to improve resolution [1]. However, they tend to be power hungry or require analog-intensive circuitry as they convert signals from the time domain to the voltage domain in order to perform arithmetic operations. A digital PLL (DPLL) is another crucial SoC component, and low-power area-efficient DPLLs are challenging to design. This paper presents a time-domain low-power ΔΣ TDC with a time-

👥 作者与机构

Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing,

Tae-Kwang Jang, Jaejin Park, Jihyun Kim, Taeik Kim, Hojin Park Samsung Electronics, Yongin, Korea As digital CMOS technology scales to 32nm and below, small and low-voltage