⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文介绍了K超级计算机的架构，采用超过54.8万个SPARC64 VIIIfx处理器核心，实现了8.162 PetaFLOPS的峰值性能。通过6维Mesh/Torus网络高效互联，解决了大规模并行计算中核心通信和功耗平衡的挑战。
Tatsumi Nakada1, Ken Seki1, Toshiyuki Shimizu1, Naoki Shinjo1, Fumiyoshi Shoji2, Atsuya Uno2, Motoyoshi Kurokawa2 Fujitsu, Kanagawa, Japan RIKEN, Hyogo, Japan 1 2 Many high-performance CPUs employ a multicore architecture with a moderate clock frequency and wide instruction issue, including SIMD extensions, to achieve high performance while retaining a practical power consumption. As demand for supercomputer performance grows faster than the rate that improvements are made to CPU performance, the total number of cores of highend supercomputers has increased tremendously. Efficient handling of large numbers of cores is a key aspect in the design of supercomputers. Building a supercomputer with lower power consumption and significant reliability is also important from the viewpoints of cost and availability. The K computer [1] is a massively parallel supercomputer system that has over 700k cores, and is designed to achieve a performance of 10 petaFLOPS. In
Hiroyuki Miyazaki1, Yoshihiro Kusano1, Hiroshi Okano1,