A 1.5GHz 890µW Digital MDLL with 400fsrms

📋 论文概要

该论文提出了一种1.5GHz、890µW的数字MDLL（乘法延迟锁定环），实现了400fs rms的积分抖动和-55.6dBc的参考杂散。通过数字架构解决了传统数字PLL中带宽折衷导致的TDC量化误差与振荡器相位噪声抑制冲突问题。

💡 主要创新点

• 提出低功耗数字MDLL架构，在1.5GHz下仅消耗890µW，实现超低功耗时钟合成。
• 通过数字域设计有效抑制参考杂散（-55.6dBc）和电源噪声灵敏度（20fs/mV），提高时钟纯净度。

🏷 关键词

📄 原文摘要

implemented using digital phase-locked loops (DPLLs), are evolving as the preferred means for synthesizing on-chip clocks. Their main benefits include small area, reduced sensitivity to analog circuit imperfections, and easier scalability to newer processes. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise poses several design challenges. For instance, a lower bandwidth suppresses TDC quantization error but cannot adequately suppress oscillator phase noise and vice versa. Consequently, either a high-resolution TDC or a low-noise oscillator is needed to achieve low jitter at the expense of large power dissipation and area [1]. Jitter is also degraded by supply noise in the oscillator, which often limits the overall jitter performance of

👥 作者与机构

Integrated Jitter, -55.6dBc Reference Spur and, 20fs/mV Supply-Noise Sensitivity Using 1b TDC

Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu Oregon State University, Corvallis, OR Highly digital clock generator architectures, most commonly