3D-MAPS: 3D Massively Parallel Processor with Stacked Memory

📋 论文概要

提出3D-MAPS，一种通过硅通孔（TSV）技术将多核处理器与堆叠存储器集成在一起的3D大规模并行处理器。该芯片首次实现了完整功能的多核处理器与存储器堆叠，解决了3D集成中系统层面实现的关键挑战。

💡 主要创新点

• 首次实现完整功能的多核处理器与堆叠存储器的3D集成，验证了TSV技术在系统级应用的可行性。
• 采用大规模并行架构与垂直互联，显著提升处理器与存储器之间的带宽和能效。

🏷 关键词

📄 原文摘要

Mohammad Hossain1, Moongon Jung1, Ilya Khorosh1, Gokul Kumar1, Young-Joon Lee1, Dean Lewis1, Tzu-Wei Lin1, Chang Liu1, Shreepad Panth1, Mohit Pathak1, Minzhen Ren1, Guanhao Shen1, Taigon Song1, Dong Hyuk Woo1, Xin Zhao1, Joungho Kim2, Ho Choi3, Gabriel Loh1, Hsien-Hsin Lee1, Sung Kyu Lim1 Georgia Institute of Technology, Atlanta, GA KAIST, Daejeon, Korea 3 Amkor Technology, Seoul, Korea 1 2 Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors,

👥 作者与机构

Dae Hyun Kim1, Krit Athikulwongse1, Michael Healy1,