A TDC-Less ADPLL with 200-to-3200MHz Range and 3mW Power Dissipation for Mobile SoC Clocking in 22nm CMOS

📋 论文概要

该论文提出了一种无时间数字转换器(TDC)的全数字锁相环(ADPLL)用于移动SoC时钟生成，实现了200至3200MHz的宽频率范围和3mW的低功耗。通过将相位和频率检测完全数字化，解决了传统PLL在可扩展性和低功耗方面的挑战。

💡 主要创新点

• 提出无TDC的ADPLL架构，将相位和频率检测推入数字域，消除了模拟电路和TDC带来的面积与功耗开销。
• 在22nm CMOS工艺下实现了极低功耗（3mW）和宽频率范围（200-3200MHz），适用于移动SoC的始终在线场景。

🏷 关键词

📄 原文摘要

Mobile SoC designs demand a low-power clocking system to maximize battery life. The host PLL is critical since it must remain enabled to support always-on, always-connected operation. In addition, the host PLL should offer wide frequency range, low area, flexible bandwidth, scalability to future manufacturing processes, negligible lock time compared to the power-state-cycling time, and acceptable period jitter for clocking digital logic. By pushing phase and frequency detection into the digital domain, the ADPLL in Fig. 14.4.1 provides efficiency and scalability in power and area. In contrast to previous bang-bang phase detector (BBPD) ADPLL designs [1-2], the BBPD in this work acts in conjunction with the digital filter to provide frequency and phase detection with dynamic digital gain compensation. The ability to detect phase and frequency, combined with an initial binary frequency search, results

👥 作者与机构

Nathaniel August, Hyung-Jin Lee, Martin Vandepas, Rachael Parker

Intel, Portland, OR