A 3D System Prototype of an eDRAM Cache Stacked Over Processor-Like Logic Using Through-Silicon Vias

📋 论文概要

本文介绍了一种3D系统原型，通过将eDRAM缓存层堆叠在处理器逻辑层之上，并利用硅通孔（TSV）实现高带宽互连，解决了传统2D集成中互连带宽不足的问题。该原型基于IBM Power7处理器的L3缓存设计，采用45nm CMOS工艺制造。

💡 主要创新点

• 首次实现了处理器逻辑与eDRAM缓存的3D堆叠集成，利用TSV提供高密度、高带宽的层间互连，显著提升系统性能。
• 基于商用处理器（Power7）的L3缓存设计，展示了3D集成在真实处理器架构中的可行性。

🏷 关键词

📄 原文摘要

IBM Systems and Technology Group, Fishkill, NY 1 2 3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache memory is one potential application of 3DI [2]. This work describes the design and operation of a prototype of a 3D system, constructed by stacking a memory layer, built with eDRAM [3] and logic blocks from the IBM Power7TM processor L3 cache, and a “processor proxy” layer in 45nm CMOS technology [4] enhanced to include through-silicon vias (TSVs) [5]. Unlike the previously reported 3D eDRAM [6], the 3D stack described here is constructed using 50µm pitch µC4’s joining the front side of one thick chip to TSV connections on the back side of a thinned chip. TSVs are formed of Cu-filled vias that are ~20µm in diameter and <100µm deep [5]. The TSV connects a back-side µC4 landing pad to a metal layer in the standard

👥 作者与机构

Matt Wordeman1, Joel Silberman1, Gary Maier2, Michael Scheuermann1

IBM T. J. Watson, Yorktown Heights, NY