A Digitally Stabilized Type-III PLL Using Ring VCO with 1.01psrms Integrated Jitter in 65nm CMOS

📋 论文概要

该论文提出了一种数字稳定的Type-III锁相环（PLL），采用环形压控振荡器（VCO），在65nm CMOS工艺下实现了1.01psrms的集成抖动。通过粗调路径增加一个原点极点，将传统Type-II PLL转换为Type-III结构，有效降低了由于KVCO增益较大引起的电荷泵和环路滤波器相位噪声贡献，同时保持了宽调谐范围。

💡 主要创新点

• 提出Type-III PLL架构，利用粗调路径的窄带宽模拟滤波器增加原点极点，在不增加输出抖动的前提下实现宽调谐范围。
• 采用数字稳定技术，优化环路参数，进一步抑制噪声，实现低抖动性能。

🏷 关键词

📄 原文摘要

control gain, KVCO, increases the phase noise contribution arising from the charge pump and loop filter. To resolve this problem, dual-tuning PLLs (DT-PLLs) have been studied [1-4]. The DT-PLL structure adds a narrow-bandwidth coarse (high-KVCO) path to the fine (low-KVCO) path consisting of a type-II PLL. The narrow-bandwidth analog filter in the coarse path plays an important role in preventing the charge pump and the loop filter from increasing the output jitter, while a wide-tuning range is maintained. Moreover, the coarse path adds another pole at origin to the fine path and transforms it from a type-II to type-III PLL [3-4]. Compared to a type-II PLL, owing to its boosted low-frequency loop gain, a type-III PLL can better suppress a low-frequency disturbance to the ring VCO, such as temperature drift. However, a type-III PLL has stability problems. To

👥 作者与机构

Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura

Toshiba, Kawasaki, Japan The design of low-jitter VCO-based PLLs is quite challenging as high VCO