A 6.7MHz-to-1.24GHz 0.0318mm2 Fast-Locking All-Digital DLL in 90nm CMOS

📋 论文概要

该论文提出了一种在90nm CMOS工艺下实现的全数字延迟锁定环（ADDLL），工作频率范围为6.7MHz至1.24GHz，核心面积仅为0.0318mm²。通过创新的电路设计解决了传统模拟DLL在先进工艺下面临的高漏电流、低电源电压等问题，并实现了快速锁定和宽频率范围。

💡 主要创新点

• 提出了一种面积高效的全数字DLL架构，通过优化延迟单元和数字控制逻辑，在宽频率范围内实现了极小的芯片面积（0.0318mm²）。
• 实现了快速锁定机制，能够在宽频率范围内快速达到锁定状态，适用于高性能数字系统的同步需求。

🏷 关键词

📄 原文摘要

synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, many designers have shifted their focus to digitally-assisted or all-digitally implemented DLLs, which are easier to design for wide range and fast-locking requirements. Due to the need for wide operating frequency range applications in all-digital DLLs (ADDLLs), many delay cells are normally deployed. As a result, a large portion of the die area is consumed by the delay cells. To address this issue, we develop a phase-tracing delay unit (PTDU) technique to reduce delay-cell usage and achieve low area and low power. In this paper, a 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking ADDLL based on the PTDU method is realized in 90nm CMOS technology.

👥 作者与机构

Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen

National Taiwan University, Taipei, Taiwan Delay-locked loops (DLLs) are widely adopted for clock generation and