Carlos Tokunaga1, Ram K. Krishnamurthy1, James W. Tschanz1 Intel, Hillsboro, OR, 2Intel, Austin, TX, 3Intel, Santa Clara, CA 1 Abstract A manycore DNN processor leverages hybrid bonding in a 14×4×2 mesh network on chip to increase 3D bandwidth between cores, accelerators, and SRAM to 2.5Tb/s/mm2. Memory throughput is improved by 39% compared to an equivalent 2D design with the same memory capacity. The 56 16×16 INT8 systolic array accelerators are stacked on top of 56 RISC-V cores to enable a peak AI performance density of 12.1TOPS/mm2. The DNN processor scores a latency of 53ms on the image classification benchmark from MLPerf. AI and machine-learning workloads feature dense data movement and high-bandwidth communication between cores, accelerators, and memory. Reducing the power and performance overhead of this data movement is key for energy-efficient operation. As die area increases, cross-die communication can become a critical bottleneck, limiting workload
Phil C. Knag1, Gregory K. Chen1, Shanshan Xie2, Satish Yada1, Wei Wu1, Yu-Shiang Lin1, Alexander Kashirin1, Xiemei Meng2, Russell Criss1, Ana Sonia Leon3,