A 0.008mm2 16-to-1600MHz All-Digital Fractional Divider Using AUX-DLL for Background LMS-Based DTC Calibration

📋 论文概要

该论文提出了一种全数字高性能独立分数分频器，利用紧凑的辅助延迟锁定环实现基于LMS的DTC背景校准，无需复制电路。该设计在0.008mm²面积内实现了16-1600MHz的宽输出频率范围和50位精细频率分辨率，最差情况下的集成抖动为350fsrms。

💡 主要创新点

• 提出了一种基于辅助延迟锁定环的LMS背景校准技术，用于数字时间转换器，无需复制电路，从而节省面积并提高鲁棒性。
• 实现了全数字、独立的高性能分数分频器，具有极宽的频率范围和精细的频率分辨率，同时占用极小的芯片面积。

🏷 关键词

📄 原文摘要

Abstract An all-digital high-performance standalone fractional divider (FDIV) is presented. It leverages a robust replica-free least-mean square (LMS)-based digital-to-time converter (DTC) background calibration using a compact auxiliary delay locked loop (AUX-DLL). The proposed FDIV provides a wide output frequency range (16-1600MHz) with very fine frequency resolution (50b) and achieves worst-case integrated jitter performance of 350fsrms, while occupying only 0.008mm2. Modern system-on-chips (SoCs) demand compact, multi-output, low-power and low-jitter clock generators. Traditional approaches using multiple phase-locked loops (PLLs), increase silicon area, power consumption and system complexity. As an effective alternative, standalone open-loop fractional dividers (FDIVs) have been introduced to generate multiple clock frequencies from a single PLL [1]. An FDIV typically integrates a multi-modulus divider

👥 作者与机构

Ahmed Elkholy, Yousr Ismail, Zhi Huang, Adesh Garg, Ali Nazemi, Jun Cao, Afshin Momtaz

Broadcom, Irvine, CA