A 3nm, 400TOPS, 1080k DMIPS SoC with Chiplet Support for ASIL D Automotive Cross-Domain Applications

📋 论文概要

本文提出了一款面向软件定义汽车的3nm SoC，集成了1080k DMIPS的APU、400TOPS的NPU和51.2GB/s片间带宽，通过RegionID-based FFI over UCIe实现功能隔离，并采用细粒度门控和层次化mCPGs等技术提升能效与可靠性，支持ASIL D功能安全等级。

💡 主要创新点

• 提出RegionID-based FFI（Freedom From Interference）机制，基于UCIe实现跨芯片的功能安全隔离。
• 采用超过90个电源域的细粒度门控，并结合增强IR-drop控制和ASIL D兼容的双核锁步（DCLS）设计。
• 引入层次化多级时钟门控（mCPGs）以减少时钟延迟，并支持Sentry和CPD低功耗模式。

🏷 关键词

📄 原文摘要

Paris, France 1 Abstract This paper presents a 3nm SoC, designed for software defined vehicles, integrating various functions for zone-based computing. The chip includes a 1,080kDMIPS APU, 400TOPS NPU and 51.2GB/s inter-chip bandwidth. Functional safety is ensured by RegionID-based FFI over UCIe. Power efficiency is achieved with fine-gating across 90+ power domains with enhanced IR-drop control and ASIL D-compliant DCLS. Hierarchical mCPGs reduce clock latency. The chip supports low-power modes such as Sentry and CPD. In recent years, the Software-Defined Vehicle (SDV) has emerged as a paradigm in the automotive industry. The SDV features a shift from domain-based to zone-based computing, supported by an Electrical/Electronic (E/E) architecture that enables seamless expansion

👥 作者与机构

Shiro Machida1, Kazuki Fukuoka1, Tomoya Onda1, Nobuhiro Yada1, Hiroyuki Nakano1, Sho Yamanaka1, Hung Van Cao2, Yusaku Hara1, Takahiro Irita1,

Kohei Wakahara1, Cyril Cordoba3, Tatsuya Kamei1, Yasuhisa Shimazaki1 Renesas Electronics, Tokyo, Japan, 2Renesas Design Vietnam, Ho Chi Minh, Vietnam, 3Renesas Electronics Europe,