A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning

📋 论文概要

本文提出一种4.75GHz数字锁相环（PLL），采用电压偏置谐波整形DCO，实现了45.8fs的积分抖动和257dB的FoM，解决了多数据转换器和收发器对低噪声频率合成的需求。

💡 主要创新点

• 提出电压偏置谐波整形DCO技术，有效抑制相位噪声，实现极低抖动。
• 通过数字化架构与先进CMOS工艺结合，在4.75GHz频率下达到257dB FoM，展示了高性能与能效的平衡。

🏷 关键词

📄 原文摘要

Simone Mattia Dartizio1, Carlo Samori1, Andrea Leonardo Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy now with Kandou Bus SA, Saint-Sulpice, Switzerland 1 2 *Equally Credited Authors (ECAs) The number of high-speed data converters and radio transceivers within the same systemon-chip (SoC) continues to grow, each requiring a dedicated low-noise frequency synthesizer. Digital PLLs (Fig. 34.3.1, top-left) are attractive solutions for low-jitter frequency synthesis, thanks to their ability to scale area and power efficiently with the availability of more advanced CMOS nodes [1-8]. The bottleneck in the synthesizer area/power optimization is often represented by the digitally controlled oscillator (DCO), whose flickerand white-noise-induced phase-noise components contribute to the synthesizer phase noise (Fig. 34.3.1, top-center). In recent years, voltage-biased DCOs have emerged as an attractive

👥 作者与机构

Stefano Gallucci*1, Francesco Tesolin*1, Pietro Salvi1, Daniele Lodi Rizzini1,

Riccardo Moleri1, Francesco Buccoleri1,2, Michele Rossoni1, Giacomo Castoro1,