A 0.021μm2 High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery

📋 论文概要

该论文提出了一种采用Intel-18A-RibbonFET工艺和PowerVia背面供电技术的高密度SRAM，实现了0.021μm²的单元面积。通过背面供电方案，解决了传统前端供电网络中VSS IR压降较大的问题，提升了供电效率。

💡 主要创新点

• 采用PowerVia背面供电技术，将VSS供电网络移至芯片背面，降低了IR压降。
• 在Intel-18A-RibbonFET工艺上实现了0.021μm²的高密度SRAM单元，显著提升了集成度。
• 通过优化供电方案，相比传统前端供电，最差情况下的VSS电阻仅增加49%，但整体供电效率更高。

🏷 关键词

📄 原文摘要

Kaushal Dave1, Arash Joushaghani1, Narae Kang1, Minwoo Ko1, Anandkumar Mahadevan Pillai2, Hema Chandra Prakash Movva1, Gyusung Park1, Muktadir Rahman1, Seenivasan Subramaniam1, Vinay Vashishtha1, Teng Yang1, Zheng Guo1, Eric A Karl1 Intel, Hillsboro, OR Intel, Santa Clara, CA 1 The worst-case VSS IR drop, for the proposed power-delivery scheme, is at the center of the array: the furthest point from PowerVias. Compared to a conventional FS-PDN, where VSS is uniformly distributed by Vias throughout the array, the proposed power scheme’s worst-case resistance is 49% more resistive for VSS R at the array center based on static IR simulations. However, the read delay of the center cell, with worst-case VSS R, is ~95% of the delay from the corner cell due to the less effective BL resistance and smaller WL delay. The VSS R for the worst-case read-delay bitcell, located at the corner, is 9% more than the

👥 作者与机构

Xiaofei Wang1, Yusung Kim1, Gwang Hyeon Baek1, Kunal Girish Bannore1,