A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an On-Chip Heater-Based Self-Trimming Technique

📋 论文概要

该论文提出一种基于片上加热器的自校准CMOS运算放大器，通过三步校准流程实现超低失调和失调漂移。解决了传统运放中温漂和工艺偏差导致的精度限制问题。

💡 主要创新点

• 提出片上加热器结合三步自校准流程，动态补偿温度引起的失调漂移，实现±5.8µV 3σ失调和±88nV/°C 3σ失调漂移。
• 利用加热器同时加热关键晶体管和恒定gm偏置电路，确保校准状态与工作状态匹配，提高补偿精度。
• 采用大尺寸输入对管（W/L=2304µm/720nm）降低1/f噪声，结合IDAC修调实现2µV LSB的高精度校准。

🏷 关键词

📄 原文摘要

important that the corresponding D0IDAC1vos code is used to ensure the opamp offset at Troom remains zero. Aodong Zhang1, Mingtao Zhan1, Mengying Chen2, Yi Zhong1, Lu Jie1, Nan Sun1, Qinwen Fan2 The trimming accuracy is eventually mainly limited by the noise of the 1st-stage opamp. Similar to [6], relatively large M1,2 (W/L = 2304µm/720nm) are chosen for a relatively low 1/f noise corner frequency (<2kHz over PVT). With ID = 210µA, the opamp’s total inputreferred noise voltage is <4µV (3σ) over PVT. The LSB of IDAC0 and IDAC1 is then chosen to be 2µV when referred to the input of the opamp, such that quantization noise is not the dominating error. To compensate for a simulated 0.41mV (3σ) input-referred opamp offset and the IDAC1 offset at Troom, IDAC0 is designed to be 9bit while IDAC1 is designed to be 6bit to compensate for a simulated 780nV/°C (3σ) input-referred offset drift. 3.4 Tsinghua University, Beijing, China

👥 作者与机构

In step three, the heater heats up M1,2 and the constant gm biasing circuit together to Thigh, resulting in an offset drift, which can be trimmed by IDAC1. For each used IDAC1 bit, it is